[PATCH] D79193: [AArch64][SVE] Implement lowering for SIGN_EXTEND etc. of SVE predicates.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:8949
+                                               SelectionDAG &DAG) const {
+  // We only request custom lowering for SVE integer vectors.
+  //
----------------
Not sure if you were aware, but we can match these extends directly to use a predicated cpy/mov immediate:

```// per-element any extend
def : Pat<(nxv16i8 (anyext (nxv16i1 PPR:$Ps1))),
          (CPY_ZPzI_B PPR:$Ps1, 0x1, 0)>;
...

// per-element sign extend
def : Pat<(nxv16i8 (sext (nxv16i1 PPR:$Ps1))),
          (CPY_ZPzI_B PPR:$Ps1, -1, 0)>;
...

// per-element zero extend
def : Pat<(nxv16i8 (zext (nxv16i1 PPR:$Ps1))),
          (CPY_ZPzI_B PPR:$Ps1, 0x1, 0)>;
...```

(For the full set of patterns, see D71712)


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D79193/new/

https://reviews.llvm.org/D79193