[llvm] 65d32a9 - [DAG] SimplifyDemandedVectorElts - remove INSERT_SUBVECTOR if we don't demand the subvector
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Fri May 1 08:27:32 PDT 2020
Author: Simon Pilgrim
Date: 2020-05-01T16:20:51+01:00
New Revision: 65d32a9892bd51c35cc3cfc1c3172c2de103a695
URL: https://github.com/llvm/llvm-project/commit/65d32a9892bd51c35cc3cfc1c3172c2de103a695
DIFF: https://github.com/llvm/llvm-project/commit/65d32a9892bd51c35cc3cfc1c3172c2de103a695.diff
LOG: [DAG] SimplifyDemandedVectorElts - remove INSERT_SUBVECTOR if we don't demand the subvector
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/test/CodeGen/X86/horizontal-reduce-smin.ll
llvm/test/CodeGen/X86/vector-reduce-smin.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 93650af3b722..b1bf1b7c4d2d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -2416,6 +2416,8 @@ bool TargetLowering::SimplifyDemandedVectorElts(
break;
unsigned SubIdx = Idx.getZExtValue();
APInt SubElts = DemandedElts.extractBits(NumSubElts, SubIdx);
+ if (!SubElts)
+ return TLO.CombineTo(Op, Base);
APInt SubUndef, SubZero;
if (SimplifyDemandedVectorElts(Sub, SubElts, SubUndef, SubZero, TLO,
Depth + 1))
diff --git a/llvm/test/CodeGen/X86/horizontal-reduce-smin.ll b/llvm/test/CodeGen/X86/horizontal-reduce-smin.ll
index 7867b5306bf7..987da0f68082 100644
--- a/llvm/test/CodeGen/X86/horizontal-reduce-smin.ll
+++ b/llvm/test/CodeGen/X86/horizontal-reduce-smin.ll
@@ -1118,14 +1118,14 @@ define i64 @test_reduce_v8i64(<8 x i64> %a0) {
;
; X86-AVX1-LABEL: test_reduce_v8i64:
; X86-AVX1: ## %bb.0:
+; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; X86-AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
+; X86-AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm4
+; X86-AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm5
+; X86-AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm1, %xmm0
+; X86-AVX1-NEXT: vblendvpd %xmm4, %xmm2, %xmm3, %xmm1
; X86-AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
-; X86-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
-; X86-AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4
-; X86-AVX1-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm5
-; X86-AVX1-NEXT: vblendvpd %xmm5, %xmm3, %xmm4, %xmm3
; X86-AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; X86-AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm1
-; X86-AVX1-NEXT: vblendvpd %xmm1, %xmm0, %xmm3, %xmm0
; X86-AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X86-AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
; X86-AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
@@ -1236,14 +1236,14 @@ define i64 @test_reduce_v8i64(<8 x i64> %a0) {
;
; X64-AVX1-LABEL: test_reduce_v8i64:
; X64-AVX1: ## %bb.0:
+; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; X64-AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
+; X64-AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm4
+; X64-AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm5
+; X64-AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm1, %xmm0
+; X64-AVX1-NEXT: vblendvpd %xmm4, %xmm2, %xmm3, %xmm1
; X64-AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
-; X64-AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
-; X64-AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4
-; X64-AVX1-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm5
-; X64-AVX1-NEXT: vblendvpd %xmm5, %xmm3, %xmm4, %xmm3
; X64-AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; X64-AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm1
-; X64-AVX1-NEXT: vblendvpd %xmm1, %xmm0, %xmm3, %xmm0
; X64-AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
; X64-AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
; X64-AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
diff --git a/llvm/test/CodeGen/X86/vector-reduce-smin.ll b/llvm/test/CodeGen/X86/vector-reduce-smin.ll
index 47a6ac4ce45d..e8259e147133 100644
--- a/llvm/test/CodeGen/X86/vector-reduce-smin.ll
+++ b/llvm/test/CodeGen/X86/vector-reduce-smin.ll
@@ -352,14 +352,14 @@ define i64 @test_v8i64(<8 x i64> %a0) {
;
; AVX1-LABEL: test_v8i64:
; AVX1: # %bb.0:
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2
+; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm3
+; AVX1-NEXT: vpcmpgtq %xmm2, %xmm3, %xmm4
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm5
+; AVX1-NEXT: vblendvpd %xmm5, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vblendvpd %xmm4, %xmm2, %xmm3, %xmm1
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm3
-; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4
-; AVX1-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm1
-; AVX1-NEXT: vblendvpd %xmm1, %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
@@ -663,24 +663,24 @@ define i64 @test_v16i64(<16 x i64> %a0) {
;
; AVX1-LABEL: test_v16i64:
; AVX1: # %bb.0:
+; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm8
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm9
; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm11
-; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm5
-; AVX1-NEXT: vpcmpgtq %xmm11, %xmm5, %xmm8
-; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm7
-; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm6
-; AVX1-NEXT: vpcmpgtq %xmm7, %xmm6, %xmm9
-; AVX1-NEXT: vpcmpgtq %xmm1, %xmm3, %xmm10
-; AVX1-NEXT: vpcmpgtq %xmm0, %xmm2, %xmm4
-; AVX1-NEXT: vblendvpd %xmm4, %xmm0, %xmm2, %xmm0
-; AVX1-NEXT: vblendvpd %xmm10, %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vextractf128 $1, %ymm3, %xmm7
+; AVX1-NEXT: vpcmpgtq %xmm11, %xmm7, %xmm10
+; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm5
+; AVX1-NEXT: vextractf128 $1, %ymm2, %xmm4
+; AVX1-NEXT: vpcmpgtq %xmm5, %xmm4, %xmm6
+; AVX1-NEXT: vblendvpd %xmm6, %xmm5, %xmm4, %xmm4
+; AVX1-NEXT: vblendvpd %xmm10, %xmm11, %xmm7, %xmm5
+; AVX1-NEXT: vpcmpgtq %xmm4, %xmm5, %xmm6
+; AVX1-NEXT: vblendvpd %xmm9, %xmm0, %xmm2, %xmm0
+; AVX1-NEXT: vblendvpd %xmm8, %xmm1, %xmm3, %xmm1
+; AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
+; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+; AVX1-NEXT: vblendvpd %xmm6, %xmm4, %xmm5, %xmm1
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
-; AVX1-NEXT: vblendvpd %xmm9, %xmm7, %xmm6, %xmm3
-; AVX1-NEXT: vblendvpd %xmm8, %xmm11, %xmm5, %xmm4
-; AVX1-NEXT: vpcmpgtq %xmm3, %xmm4, %xmm5
-; AVX1-NEXT: vblendvpd %xmm5, %xmm3, %xmm4, %xmm3
; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
-; AVX1-NEXT: vpcmpgtq %xmm0, %xmm3, %xmm1
-; AVX1-NEXT: vblendvpd %xmm1, %xmm0, %xmm3, %xmm0
; AVX1-NEXT: vpermilps {{.*#+}} xmm1 = xmm0[2,3,0,1]
; AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm2
; AVX1-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
More information about the llvm-commits
mailing list