[PATCH] D78206: [Target][ARM] Make Low Overhead Loops coexist with VPT blocks
Sam Parker via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri May 1 03:01:44 PDT 2020
samparker added a comment.
Sorry, I forgot about this. Thanks for that example, I now see how the VCTP can be Else predicated, but I obviously don't quite understand how VPT predication works! The code below is what is generated from the example and now I don't understand why the VSTR is Else predicated. Is it because it needs the same inverted predicate as the VCTP, coming from the VCMP, as well as being ANDed with the VCTP? My intuition wanted it to be Then predicated after the VCTP has already done an inversion.
vctp.32 r1
vpst
vldrwt.u32 q1, [r0]
vptee.s32 ge, q1, r2
vcmpt.s32 le, q1, r3
vctpe.32 r1
vstrwe.32 q0, [r0], #16
subs r1, #4
le lr, .LBB0_1
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D78206/new/
https://reviews.llvm.org/D78206
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