[PATCH] D79187: [DAGCombiner] fold (fp_round (int_to_fp X)) -> (int_to_fp X)

[Sam Elliott via Phabricator via llvm-commits]

lenary created this revision.
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This is a follow-up to D78906 <https://reviews.llvm.org/D78906> which moves the required fold from a SelectionDAG
pattern into a (target-independent) DAGCombiner fold.

I believe the fold is valid if result type of the round can still accurately
represent the original integer type (signed or unsigned), and the intermediate
fp type is wider than the resulting fp type.

An example from these tests is where the original integer type is i32, the
intermediate float type is double, and the resulting fp type is float. My
understanding in this case is that the fp_round removes as much information as
just doing the int_to_fp directly.

The advantage of doing it in the DAGCombiner in this case is that it allows the
fold to happen, even if the intermediate floating point value is not a legal
type. In that case, the legaliser will turn the round and the int_to_fp into two
separate libcalls, before patterns can be used. The DAGCombiner does not have
this issue, as it is run before legalisation.

This patch needs a thorough review with respect to FP semantics. I am not
particularly familiar with how rounding and the like will affect this fold, and
I did find it hard to get the fold conditions correct to avoid infinite loops in
the AArch64 backend (which affected fp16 types), but to have the optimisation
work on the examples I expected in the RISC-V backend.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D79187

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
  llvm/lib/Target/RISCV/RISCVInstrInfoF.td
  llvm/test/CodeGen/RISCV/fp-convert-indirect.ll

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