[PATCH] D79096: [SelectionDAG] Unify scalarizeVectorLoad and VectorLegalizer::ExpandLoad

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:6604
+
+    // Load the whole vector including the padding bits. This avoids inserting
+    // extra bit masking that makes the codegen worse.
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This comment doesn't completely make sense. The memory VT is still based on NumSrcBits so it isn't loading the padding bits.


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Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:6620
+      SDValue Elt =
+          DAG.getNode(ISD::AND, SL, LoadVT, ShiftedElt, SrcEltBitMask);
+      SDValue Scalar = DAG.getNode(ISD::TRUNCATE, SL, SrcEltVT, Elt);
----------------
Why do we need to AND before the TRUNCATE? Isn't the AND masking to the same number of bits as the truncate?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D79096/new/

https://reviews.llvm.org/D79096