[llvm] 51308ee - [X86] Extend combine-bitselect tests
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 30 08:32:05 PDT 2020
Author: Simon Pilgrim
Date: 2020-04-30T16:24:17+01:00
New Revision: 51308ee30ce78d643d93ed08be0bb11fb7c98289
URL: https://github.com/llvm/llvm-project/commit/51308ee30ce78d643d93ed08be0bb11fb7c98289
DIFF: https://github.com/llvm/llvm-project/commit/51308ee30ce78d643d93ed08be0bb11fb7c98289.diff
LOG: [X86] Extend combine-bitselect tests
Add AVX512VL tests and v2i64/v8i64 mask broadcast tests that match the existing v4i64 versions
Added:
Modified:
llvm/test/CodeGen/X86/combine-bitselect.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/X86/combine-bitselect.ll b/llvm/test/CodeGen/X86/combine-bitselect.ll
index 1fc18357ef7c..bd4c65b77197 100644
--- a/llvm/test/CodeGen/X86/combine-bitselect.ll
+++ b/llvm/test/CodeGen/X86/combine-bitselect.ll
@@ -3,7 +3,8 @@
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+xop | FileCheck %s --check-prefixes=XOP
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=AVX,AVX1
; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=AVX,AVX2
-; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX,AVX512F
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefixes=AVX512,AVX512F
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512vl | FileCheck %s --check-prefixes=AVX512,AVX512VL
;
; 128-bit vectors
@@ -28,6 +29,18 @@ define <2 x i64> @bitselect_v2i64_rr(<2 x i64>, <2 x i64>) {
; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vorps %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq
+;
+; AVX512F-LABEL: bitselect_v2i64_rr:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vorps %xmm0, %xmm1, %xmm0
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: bitselect_v2i64_rr:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %xmm1, %xmm0
+; AVX512VL-NEXT: retq
%3 = and <2 x i64> %0, <i64 4294967296, i64 12884901890>
%4 = and <2 x i64> %1, <i64 -4294967297, i64 -12884901891>
%5 = or <2 x i64> %4, %3
@@ -56,6 +69,20 @@ define <2 x i64> @bitselect_v2i64_rm(<2 x i64>, <2 x i64>* nocapture readonly) {
; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vorps %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq
+;
+; AVX512F-LABEL: bitselect_v2i64_rm:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vmovaps (%rdi), %xmm1
+; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vorps %xmm0, %xmm1, %xmm0
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: bitselect_v2i64_rm:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vmovdqa (%rdi), %xmm1
+; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %xmm1, %xmm0
+; AVX512VL-NEXT: retq
%3 = load <2 x i64>, <2 x i64>* %1
%4 = and <2 x i64> %0, <i64 8589934593, i64 3>
%5 = and <2 x i64> %3, <i64 -8589934594, i64 -4>
@@ -85,6 +112,20 @@ define <2 x i64> @bitselect_v2i64_mr(<2 x i64>* nocapture readonly, <2 x i64>) {
; AVX-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
; AVX-NEXT: vorps %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq
+;
+; AVX512F-LABEL: bitselect_v2i64_mr:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vmovaps (%rdi), %xmm1
+; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vorps %xmm0, %xmm1, %xmm0
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: bitselect_v2i64_mr:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vmovdqa (%rdi), %xmm1
+; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %xmm1, %xmm0
+; AVX512VL-NEXT: retq
%3 = load <2 x i64>, <2 x i64>* %0
%4 = and <2 x i64> %3, <i64 12884901890, i64 4294967296>
%5 = and <2 x i64> %1, <i64 -12884901891, i64 -4294967297>
@@ -117,6 +158,22 @@ define <2 x i64> @bitselect_v2i64_mm(<2 x i64>* nocapture readonly, <2 x i64>* n
; AVX-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
; AVX-NEXT: vorps %xmm0, %xmm1, %xmm0
; AVX-NEXT: retq
+;
+; AVX512F-LABEL: bitselect_v2i64_mm:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vmovaps (%rdi), %xmm0
+; AVX512F-NEXT: vmovaps (%rsi), %xmm1
+; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm0, %xmm0
+; AVX512F-NEXT: vandps {{.*}}(%rip), %xmm1, %xmm1
+; AVX512F-NEXT: vorps %xmm0, %xmm1, %xmm0
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: bitselect_v2i64_mm:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vmovdqa (%rsi), %xmm1
+; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm0 = [18446744073709551612,18446744065119617022]
+; AVX512VL-NEXT: vpternlogq $202, (%rdi), %xmm1, %xmm0
+; AVX512VL-NEXT: retq
%3 = load <2 x i64>, <2 x i64>* %0
%4 = load <2 x i64>, <2 x i64>* %1
%5 = and <2 x i64> %3, <i64 3, i64 8589934593>
@@ -125,6 +182,144 @@ define <2 x i64> @bitselect_v2i64_mm(<2 x i64>* nocapture readonly, <2 x i64>* n
ret <2 x i64> %7
}
+define <2 x i64> @bitselect_v2i64_broadcast_rrr(<2 x i64> %a0, <2 x i64> %a1, i64 %a2) {
+; SSE-LABEL: bitselect_v2i64_broadcast_rrr:
+; SSE: # %bb.0:
+; SSE-NEXT: movq %rdi, %xmm2
+; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,1,0,1]
+; SSE-NEXT: pcmpeqd %xmm4, %xmm4
+; SSE-NEXT: pxor %xmm2, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm4[0,1,0,1]
+; SSE-NEXT: pand %xmm3, %xmm0
+; SSE-NEXT: pand %xmm1, %xmm2
+; SSE-NEXT: por %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; XOP-LABEL: bitselect_v2i64_broadcast_rrr:
+; XOP: # %bb.0:
+; XOP-NEXT: vmovq %rdi, %xmm2
+; XOP-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[0,1,0,1]
+; XOP-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
+; XOP-NEXT: vpxor %xmm4, %xmm2, %xmm2
+; XOP-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,1,0,1]
+; XOP-NEXT: vpand %xmm3, %xmm0, %xmm0
+; XOP-NEXT: vpand %xmm2, %xmm1, %xmm1
+; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0
+; XOP-NEXT: retq
+;
+; AVX1-LABEL: bitselect_v2i64_broadcast_rrr:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovq %rdi, %xmm2
+; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[0,1,0,1]
+; AVX1-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
+; AVX1-NEXT: vpxor %xmm4, %xmm2, %xmm2
+; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,1,0,1]
+; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
+; AVX1-NEXT: vpand %xmm2, %xmm1, %xmm1
+; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: bitselect_v2i64_broadcast_rrr:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovq %rdi, %xmm2
+; AVX2-NEXT: vpbroadcastq %xmm2, %xmm2
+; AVX2-NEXT: vpand %xmm2, %xmm0, %xmm0
+; AVX2-NEXT: vpandn %xmm1, %xmm2, %xmm1
+; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: bitselect_v2i64_broadcast_rrr:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vmovq %rdi, %xmm2
+; AVX512F-NEXT: vpbroadcastq %xmm2, %xmm2
+; AVX512F-NEXT: vpand %xmm2, %xmm0, %xmm0
+; AVX512F-NEXT: vpandn %xmm1, %xmm2, %xmm1
+; AVX512F-NEXT: vpor %xmm1, %xmm0, %xmm0
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: bitselect_v2i64_broadcast_rrr:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpbroadcastq %rdi, %xmm2
+; AVX512VL-NEXT: vpternlogq $226, %xmm1, %xmm2, %xmm0
+; AVX512VL-NEXT: retq
+ %1 = insertelement <2 x i64> undef, i64 %a2, i32 0
+ %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> zeroinitializer
+ %3 = xor <2 x i64> %1, <i64 -1, i64 undef>
+ %4 = shufflevector <2 x i64> %3, <2 x i64> undef, <2 x i32> zeroinitializer
+ %5 = and <2 x i64> %a0, %2
+ %6 = and <2 x i64> %a1, %4
+ %7 = or <2 x i64> %5, %6
+ ret <2 x i64> %7
+}
+
+define <2 x i64> @bitselect_v2i64_broadcast_rrm(<2 x i64> %a0, <2 x i64> %a1, i64* %p2) {
+; SSE-LABEL: bitselect_v2i64_broadcast_rrm:
+; SSE: # %bb.0:
+; SSE-NEXT: movq {{.*#+}} xmm2 = mem[0],zero
+; SSE-NEXT: pshufd {{.*#+}} xmm3 = xmm2[0,1,0,1]
+; SSE-NEXT: pcmpeqd %xmm4, %xmm4
+; SSE-NEXT: pxor %xmm2, %xmm4
+; SSE-NEXT: pshufd {{.*#+}} xmm2 = xmm4[0,1,0,1]
+; SSE-NEXT: pand %xmm3, %xmm0
+; SSE-NEXT: pand %xmm1, %xmm2
+; SSE-NEXT: por %xmm2, %xmm0
+; SSE-NEXT: retq
+;
+; XOP-LABEL: bitselect_v2i64_broadcast_rrm:
+; XOP: # %bb.0:
+; XOP-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
+; XOP-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[0,1,0,1]
+; XOP-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
+; XOP-NEXT: vpxor %xmm4, %xmm2, %xmm2
+; XOP-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,1,0,1]
+; XOP-NEXT: vpand %xmm3, %xmm0, %xmm0
+; XOP-NEXT: vpand %xmm2, %xmm1, %xmm1
+; XOP-NEXT: vpor %xmm1, %xmm0, %xmm0
+; XOP-NEXT: retq
+;
+; AVX1-LABEL: bitselect_v2i64_broadcast_rrm:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovq {{.*#+}} xmm2 = mem[0],zero
+; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[0,1,0,1]
+; AVX1-NEXT: vpcmpeqd %xmm4, %xmm4, %xmm4
+; AVX1-NEXT: vpxor %xmm4, %xmm2, %xmm2
+; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[0,1,0,1]
+; AVX1-NEXT: vpand %xmm3, %xmm0, %xmm0
+; AVX1-NEXT: vpand %xmm2, %xmm1, %xmm1
+; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: bitselect_v2i64_broadcast_rrm:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovddup {{.*#+}} xmm2 = mem[0,0]
+; AVX2-NEXT: vandps %xmm2, %xmm0, %xmm0
+; AVX2-NEXT: vandnps %xmm1, %xmm2, %xmm1
+; AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0
+; AVX2-NEXT: retq
+;
+; AVX512F-LABEL: bitselect_v2i64_broadcast_rrm:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vmovddup {{.*#+}} xmm2 = mem[0,0]
+; AVX512F-NEXT: vandps %xmm2, %xmm0, %xmm0
+; AVX512F-NEXT: vandnps %xmm1, %xmm2, %xmm1
+; AVX512F-NEXT: vorps %xmm1, %xmm0, %xmm0
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: bitselect_v2i64_broadcast_rrm:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpternlogq $228, (%rdi){1to2}, %xmm1, %xmm0
+; AVX512VL-NEXT: retq
+ %a2 = load i64, i64* %p2
+ %1 = insertelement <2 x i64> undef, i64 %a2, i32 0
+ %2 = shufflevector <2 x i64> %1, <2 x i64> undef, <2 x i32> zeroinitializer
+ %3 = xor <2 x i64> %1, <i64 -1, i64 undef>
+ %4 = shufflevector <2 x i64> %3, <2 x i64> undef, <2 x i32> zeroinitializer
+ %5 = and <2 x i64> %a0, %2
+ %6 = and <2 x i64> %a1, %4
+ %7 = or <2 x i64> %5, %6
+ ret <2 x i64> %7
+}
+
;
; 256-bit vectors
;
@@ -151,6 +346,18 @@ define <4 x i64> @bitselect_v4i64_rr(<4 x i64>, <4 x i64>) {
; AVX-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
; AVX-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX-NEXT: retq
+;
+; AVX512F-LABEL: bitselect_v4i64_rr:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vorps %ymm0, %ymm1, %ymm0
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: bitselect_v4i64_rr:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%3 = and <4 x i64> %0, <i64 4294967296, i64 12884901890, i64 12884901890, i64 12884901890>
%4 = and <4 x i64> %1, <i64 -4294967297, i64 -12884901891, i64 -12884901891, i64 -12884901891>
%5 = or <4 x i64> %4, %3
@@ -187,6 +394,20 @@ define <4 x i64> @bitselect_v4i64_rm(<4 x i64>, <4 x i64>* nocapture readonly) {
; AVX-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
; AVX-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX-NEXT: retq
+;
+; AVX512F-LABEL: bitselect_v4i64_rm:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vmovaps (%rdi), %ymm1
+; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vorps %ymm0, %ymm1, %ymm0
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: bitselect_v4i64_rm:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vmovdqa (%rdi), %ymm1
+; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%3 = load <4 x i64>, <4 x i64>* %1
%4 = and <4 x i64> %0, <i64 8589934593, i64 3, i64 8589934593, i64 3>
%5 = and <4 x i64> %3, <i64 -8589934594, i64 -4, i64 -8589934594, i64 -4>
@@ -224,6 +445,20 @@ define <4 x i64> @bitselect_v4i64_mr(<4 x i64>* nocapture readonly, <4 x i64>) {
; AVX-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
; AVX-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX-NEXT: retq
+;
+; AVX512F-LABEL: bitselect_v4i64_mr:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vmovaps (%rdi), %ymm1
+; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vorps %ymm0, %ymm1, %ymm0
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: bitselect_v4i64_mr:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vmovdqa (%rdi), %ymm1
+; AVX512VL-NEXT: vpternlogq $216, {{.*}}(%rip), %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%3 = load <4 x i64>, <4 x i64>* %0
%4 = and <4 x i64> %3, <i64 12884901890, i64 4294967296, i64 12884901890, i64 4294967296>
%5 = and <4 x i64> %1, <i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -4294967297>
@@ -261,6 +496,22 @@ define <4 x i64> @bitselect_v4i64_mm(<4 x i64>* nocapture readonly, <4 x i64>* n
; AVX-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
; AVX-NEXT: vorps %ymm0, %ymm1, %ymm0
; AVX-NEXT: retq
+;
+; AVX512F-LABEL: bitselect_v4i64_mm:
+; AVX512F: # %bb.0:
+; AVX512F-NEXT: vmovaps (%rdi), %ymm0
+; AVX512F-NEXT: vmovaps (%rsi), %ymm1
+; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm0, %ymm0
+; AVX512F-NEXT: vandps {{.*}}(%rip), %ymm1, %ymm1
+; AVX512F-NEXT: vorps %ymm0, %ymm1, %ymm0
+; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: bitselect_v4i64_mm:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vmovdqa (%rsi), %ymm1
+; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm0 = [18446744073709551612,18446744065119617022,18446744073709551612,18446744065119617022]
+; AVX512VL-NEXT: vpternlogq $202, (%rdi), %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%3 = load <4 x i64>, <4 x i64>* %0
%4 = load <4 x i64>, <4 x i64>* %1
%5 = and <4 x i64> %3, <i64 3, i64 8589934593, i64 3, i64 8589934593>
@@ -332,6 +583,12 @@ define <4 x i64> @bitselect_v4i64_broadcast_rrr(<4 x i64> %a0, <4 x i64> %a1, i6
; AVX512F-NEXT: vpandn %ymm1, %ymm2, %ymm1
; AVX512F-NEXT: vpor %ymm1, %ymm0, %ymm0
; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: bitselect_v4i64_broadcast_rrr:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpbroadcastq %rdi, %ymm2
+; AVX512VL-NEXT: vpternlogq $226, %ymm1, %ymm2, %ymm0
+; AVX512VL-NEXT: retq
%1 = insertelement <4 x i64> undef, i64 %a2, i32 0
%2 = shufflevector <4 x i64> %1, <4 x i64> undef, <4 x i32> zeroinitializer
%3 = xor <4 x i64> %1, <i64 -1, i64 undef, i64 undef, i64 undef>
@@ -401,6 +658,11 @@ define <4 x i64> @bitselect_v4i64_broadcast_rrm(<4 x i64> %a0, <4 x i64> %a1, i6
; AVX512F-NEXT: vandnps %ymm1, %ymm2, %ymm1
; AVX512F-NEXT: vorps %ymm1, %ymm0, %ymm0
; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: bitselect_v4i64_broadcast_rrm:
+; AVX512VL: # %bb.0:
+; AVX512VL-NEXT: vpternlogq $228, (%rdi){1to4}, %ymm1, %ymm0
+; AVX512VL-NEXT: retq
%a2 = load i64, i64* %p2
%1 = insertelement <4 x i64> undef, i64 %a2, i32 0
%2 = shufflevector <4 x i64> %1, <4 x i64> undef, <4 x i32> zeroinitializer
@@ -448,32 +710,21 @@ define <8 x i64> @bitselect_v8i64_rr(<8 x i64>, <8 x i64>) {
; XOP-NEXT: vpcmov %ymm4, %ymm1, %ymm3, %ymm1
; XOP-NEXT: retq
;
-; AVX1-LABEL: bitselect_v8i64_rr:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vmovaps {{.*#+}} ymm4 = [18446744069414584319,18446744060824649725,18446744060824649725,18446744060824649725]
-; AVX1-NEXT: vandps %ymm4, %ymm3, %ymm3
-; AVX1-NEXT: vandps %ymm4, %ymm2, %ymm2
-; AVX1-NEXT: vandnps %ymm0, %ymm4, %ymm0
-; AVX1-NEXT: vorps %ymm0, %ymm2, %ymm0
-; AVX1-NEXT: vandnps %ymm1, %ymm4, %ymm1
-; AVX1-NEXT: vorps %ymm1, %ymm3, %ymm1
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: bitselect_v8i64_rr:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vmovaps {{.*#+}} ymm4 = [18446744069414584319,18446744060824649725,18446744060824649725,18446744060824649725]
-; AVX2-NEXT: vandps %ymm4, %ymm3, %ymm3
-; AVX2-NEXT: vandps %ymm4, %ymm2, %ymm2
-; AVX2-NEXT: vandnps %ymm0, %ymm4, %ymm0
-; AVX2-NEXT: vorps %ymm0, %ymm2, %ymm0
-; AVX2-NEXT: vandnps %ymm1, %ymm4, %ymm1
-; AVX2-NEXT: vorps %ymm1, %ymm3, %ymm1
-; AVX2-NEXT: retq
+; AVX-LABEL: bitselect_v8i64_rr:
+; AVX: # %bb.0:
+; AVX-NEXT: vmovaps {{.*#+}} ymm4 = [18446744069414584319,18446744060824649725,18446744060824649725,18446744060824649725]
+; AVX-NEXT: vandps %ymm4, %ymm3, %ymm3
+; AVX-NEXT: vandps %ymm4, %ymm2, %ymm2
+; AVX-NEXT: vandnps %ymm0, %ymm4, %ymm0
+; AVX-NEXT: vorps %ymm0, %ymm2, %ymm0
+; AVX-NEXT: vandnps %ymm1, %ymm4, %ymm1
+; AVX-NEXT: vorps %ymm1, %ymm3, %ymm1
+; AVX-NEXT: retq
;
-; AVX512F-LABEL: bitselect_v8i64_rr:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vpternlogq $216, {{.*}}(%rip), %zmm1, %zmm0
-; AVX512F-NEXT: retq
+; AVX512-LABEL: bitselect_v8i64_rr:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpternlogq $216, {{.*}}(%rip), %zmm1, %zmm0
+; AVX512-NEXT: retq
%3 = and <8 x i64> %0, <i64 4294967296, i64 12884901890, i64 12884901890, i64 12884901890, i64 4294967296, i64 12884901890, i64 12884901890, i64 12884901890>
%4 = and <8 x i64> %1, <i64 -4294967297, i64 -12884901891, i64 -12884901891, i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -12884901891, i64 -12884901891>
%5 = or <8 x i64> %4, %3
@@ -519,35 +770,23 @@ define <8 x i64> @bitselect_v8i64_rm(<8 x i64>, <8 x i64>* nocapture readonly) {
; XOP-NEXT: vpcmov %ymm4, %ymm1, %ymm3, %ymm1
; XOP-NEXT: retq
;
-; AVX1-LABEL: bitselect_v8i64_rm:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vbroadcastf128 {{.*#+}} ymm2 = [18446744065119617022,18446744073709551612,18446744065119617022,18446744073709551612]
-; AVX1-NEXT: # ymm2 = mem[0,1,0,1]
-; AVX1-NEXT: vandps 32(%rdi), %ymm2, %ymm3
-; AVX1-NEXT: vandps (%rdi), %ymm2, %ymm4
-; AVX1-NEXT: vandnps %ymm0, %ymm2, %ymm0
-; AVX1-NEXT: vorps %ymm0, %ymm4, %ymm0
-; AVX1-NEXT: vandnps %ymm1, %ymm2, %ymm1
-; AVX1-NEXT: vorps %ymm1, %ymm3, %ymm1
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: bitselect_v8i64_rm:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm2 = [18446744065119617022,18446744073709551612,18446744065119617022,18446744073709551612]
-; AVX2-NEXT: # ymm2 = mem[0,1,0,1]
-; AVX2-NEXT: vandps 32(%rdi), %ymm2, %ymm3
-; AVX2-NEXT: vandps (%rdi), %ymm2, %ymm4
-; AVX2-NEXT: vandnps %ymm0, %ymm2, %ymm0
-; AVX2-NEXT: vorps %ymm0, %ymm4, %ymm0
-; AVX2-NEXT: vandnps %ymm1, %ymm2, %ymm1
-; AVX2-NEXT: vorps %ymm1, %ymm3, %ymm1
-; AVX2-NEXT: retq
+; AVX-LABEL: bitselect_v8i64_rm:
+; AVX: # %bb.0:
+; AVX-NEXT: vbroadcastf128 {{.*#+}} ymm2 = [18446744065119617022,18446744073709551612,18446744065119617022,18446744073709551612]
+; AVX-NEXT: # ymm2 = mem[0,1,0,1]
+; AVX-NEXT: vandps 32(%rdi), %ymm2, %ymm3
+; AVX-NEXT: vandps (%rdi), %ymm2, %ymm4
+; AVX-NEXT: vandnps %ymm0, %ymm2, %ymm0
+; AVX-NEXT: vorps %ymm0, %ymm4, %ymm0
+; AVX-NEXT: vandnps %ymm1, %ymm2, %ymm1
+; AVX-NEXT: vorps %ymm1, %ymm3, %ymm1
+; AVX-NEXT: retq
;
-; AVX512F-LABEL: bitselect_v8i64_rm:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovdqa64 (%rdi), %zmm1
-; AVX512F-NEXT: vpternlogq $216, {{.*}}(%rip), %zmm1, %zmm0
-; AVX512F-NEXT: retq
+; AVX512-LABEL: bitselect_v8i64_rm:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vmovdqa64 (%rdi), %zmm1
+; AVX512-NEXT: vpternlogq $216, {{.*}}(%rip), %zmm1, %zmm0
+; AVX512-NEXT: retq
%3 = load <8 x i64>, <8 x i64>* %1
%4 = and <8 x i64> %0, <i64 8589934593, i64 3, i64 8589934593, i64 3, i64 8589934593, i64 3, i64 8589934593, i64 3>
%5 = and <8 x i64> %3, <i64 -8589934594, i64 -4, i64 -8589934594, i64 -4, i64 -8589934594, i64 -4, i64 -8589934594, i64 -4>
@@ -594,35 +833,23 @@ define <8 x i64> @bitselect_v8i64_mr(<8 x i64>* nocapture readonly, <8 x i64>) {
; XOP-NEXT: vpcmov %ymm4, %ymm1, %ymm3, %ymm1
; XOP-NEXT: retq
;
-; AVX1-LABEL: bitselect_v8i64_mr:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vbroadcastf128 {{.*#+}} ymm2 = [12884901890,4294967296,12884901890,4294967296]
-; AVX1-NEXT: # ymm2 = mem[0,1,0,1]
-; AVX1-NEXT: vandps 32(%rdi), %ymm2, %ymm3
-; AVX1-NEXT: vandps (%rdi), %ymm2, %ymm4
-; AVX1-NEXT: vandnps %ymm0, %ymm2, %ymm0
-; AVX1-NEXT: vorps %ymm0, %ymm4, %ymm0
-; AVX1-NEXT: vandnps %ymm1, %ymm2, %ymm1
-; AVX1-NEXT: vorps %ymm1, %ymm3, %ymm1
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: bitselect_v8i64_mr:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm2 = [12884901890,4294967296,12884901890,4294967296]
-; AVX2-NEXT: # ymm2 = mem[0,1,0,1]
-; AVX2-NEXT: vandps 32(%rdi), %ymm2, %ymm3
-; AVX2-NEXT: vandps (%rdi), %ymm2, %ymm4
-; AVX2-NEXT: vandnps %ymm0, %ymm2, %ymm0
-; AVX2-NEXT: vorps %ymm0, %ymm4, %ymm0
-; AVX2-NEXT: vandnps %ymm1, %ymm2, %ymm1
-; AVX2-NEXT: vorps %ymm1, %ymm3, %ymm1
-; AVX2-NEXT: retq
+; AVX-LABEL: bitselect_v8i64_mr:
+; AVX: # %bb.0:
+; AVX-NEXT: vbroadcastf128 {{.*#+}} ymm2 = [12884901890,4294967296,12884901890,4294967296]
+; AVX-NEXT: # ymm2 = mem[0,1,0,1]
+; AVX-NEXT: vandps 32(%rdi), %ymm2, %ymm3
+; AVX-NEXT: vandps (%rdi), %ymm2, %ymm4
+; AVX-NEXT: vandnps %ymm0, %ymm2, %ymm0
+; AVX-NEXT: vorps %ymm0, %ymm4, %ymm0
+; AVX-NEXT: vandnps %ymm1, %ymm2, %ymm1
+; AVX-NEXT: vorps %ymm1, %ymm3, %ymm1
+; AVX-NEXT: retq
;
-; AVX512F-LABEL: bitselect_v8i64_mr:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovdqa64 (%rdi), %zmm1
-; AVX512F-NEXT: vpternlogq $216, {{.*}}(%rip), %zmm1, %zmm0
-; AVX512F-NEXT: retq
+; AVX512-LABEL: bitselect_v8i64_mr:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vmovdqa64 (%rdi), %zmm1
+; AVX512-NEXT: vpternlogq $216, {{.*}}(%rip), %zmm1, %zmm0
+; AVX512-NEXT: retq
%3 = load <8 x i64>, <8 x i64>* %0
%4 = and <8 x i64> %3, <i64 12884901890, i64 4294967296, i64 12884901890, i64 4294967296, i64 12884901890, i64 4294967296, i64 12884901890, i64 4294967296>
%5 = and <8 x i64> %1, <i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -4294967297, i64 -12884901891, i64 -4294967297>
@@ -665,36 +892,24 @@ define <8 x i64> @bitselect_v8i64_mm(<8 x i64>* nocapture readonly, <8 x i64>* n
; XOP-NEXT: vpcmov %ymm2, 32(%rdi), %ymm1, %ymm1
; XOP-NEXT: retq
;
-; AVX1-LABEL: bitselect_v8i64_mm:
-; AVX1: # %bb.0:
-; AVX1-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [18446744073709551612,18446744065119617022,18446744073709551612,18446744065119617022]
-; AVX1-NEXT: # ymm1 = mem[0,1,0,1]
-; AVX1-NEXT: vandps 32(%rsi), %ymm1, %ymm2
-; AVX1-NEXT: vandps (%rsi), %ymm1, %ymm0
-; AVX1-NEXT: vandnps (%rdi), %ymm1, %ymm3
-; AVX1-NEXT: vorps %ymm3, %ymm0, %ymm0
-; AVX1-NEXT: vandnps 32(%rdi), %ymm1, %ymm1
-; AVX1-NEXT: vorps %ymm1, %ymm2, %ymm1
-; AVX1-NEXT: retq
-;
-; AVX2-LABEL: bitselect_v8i64_mm:
-; AVX2: # %bb.0:
-; AVX2-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [18446744073709551612,18446744065119617022,18446744073709551612,18446744065119617022]
-; AVX2-NEXT: # ymm1 = mem[0,1,0,1]
-; AVX2-NEXT: vandps 32(%rsi), %ymm1, %ymm2
-; AVX2-NEXT: vandps (%rsi), %ymm1, %ymm0
-; AVX2-NEXT: vandnps (%rdi), %ymm1, %ymm3
-; AVX2-NEXT: vorps %ymm3, %ymm0, %ymm0
-; AVX2-NEXT: vandnps 32(%rdi), %ymm1, %ymm1
-; AVX2-NEXT: vorps %ymm1, %ymm2, %ymm1
-; AVX2-NEXT: retq
+; AVX-LABEL: bitselect_v8i64_mm:
+; AVX: # %bb.0:
+; AVX-NEXT: vbroadcastf128 {{.*#+}} ymm1 = [18446744073709551612,18446744065119617022,18446744073709551612,18446744065119617022]
+; AVX-NEXT: # ymm1 = mem[0,1,0,1]
+; AVX-NEXT: vandps 32(%rsi), %ymm1, %ymm2
+; AVX-NEXT: vandps (%rsi), %ymm1, %ymm0
+; AVX-NEXT: vandnps (%rdi), %ymm1, %ymm3
+; AVX-NEXT: vorps %ymm3, %ymm0, %ymm0
+; AVX-NEXT: vandnps 32(%rdi), %ymm1, %ymm1
+; AVX-NEXT: vorps %ymm1, %ymm2, %ymm1
+; AVX-NEXT: retq
;
-; AVX512F-LABEL: bitselect_v8i64_mm:
-; AVX512F: # %bb.0:
-; AVX512F-NEXT: vmovdqa64 (%rsi), %zmm1
-; AVX512F-NEXT: vmovdqa64 {{.*#+}} zmm0 = [18446744073709551612,18446744065119617022,18446744073709551612,18446744065119617022,18446744073709551612,18446744065119617022,18446744073709551612,18446744065119617022]
-; AVX512F-NEXT: vpternlogq $202, (%rdi), %zmm1, %zmm0
-; AVX512F-NEXT: retq
+; AVX512-LABEL: bitselect_v8i64_mm:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vmovdqa64 (%rsi), %zmm1
+; AVX512-NEXT: vmovdqa64 {{.*#+}} zmm0 = [18446744073709551612,18446744065119617022,18446744073709551612,18446744065119617022,18446744073709551612,18446744065119617022,18446744073709551612,18446744065119617022]
+; AVX512-NEXT: vpternlogq $202, (%rdi), %zmm1, %zmm0
+; AVX512-NEXT: retq
%3 = load <8 x i64>, <8 x i64>* %0
%4 = load <8 x i64>, <8 x i64>* %1
%5 = and <8 x i64> %3, <i64 3, i64 8589934593, i64 3, i64 8589934593, i64 3, i64 8589934593, i64 3, i64 8589934593>
@@ -703,6 +918,173 @@ define <8 x i64> @bitselect_v8i64_mm(<8 x i64>* nocapture readonly, <8 x i64>* n
ret <8 x i64> %7
}
+define <8 x i64> @bitselect_v8i64_broadcast_rrr(<8 x i64> %a0, <8 x i64> %a1, i64 %a2) {
+; SSE-LABEL: bitselect_v8i64_broadcast_rrr:
+; SSE: # %bb.0:
+; SSE-NEXT: movq %rdi, %xmm8
+; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm8[0,1,0,1]
+; SSE-NEXT: pcmpeqd %xmm10, %xmm10
+; SSE-NEXT: pxor %xmm8, %xmm10
+; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm10[0,1,0,1]
+; SSE-NEXT: pand %xmm9, %xmm3
+; SSE-NEXT: pand %xmm9, %xmm2
+; SSE-NEXT: pand %xmm9, %xmm1
+; SSE-NEXT: pand %xmm9, %xmm0
+; SSE-NEXT: pand %xmm8, %xmm7
+; SSE-NEXT: por %xmm7, %xmm3
+; SSE-NEXT: pand %xmm8, %xmm6
+; SSE-NEXT: por %xmm6, %xmm2
+; SSE-NEXT: pand %xmm8, %xmm5
+; SSE-NEXT: por %xmm5, %xmm1
+; SSE-NEXT: pand %xmm8, %xmm4
+; SSE-NEXT: por %xmm4, %xmm0
+; SSE-NEXT: retq
+;
+; XOP-LABEL: bitselect_v8i64_broadcast_rrr:
+; XOP: # %bb.0:
+; XOP-NEXT: vmovq %rdi, %xmm4
+; XOP-NEXT: vmovq %rdi, %xmm5
+; XOP-NEXT: vmovddup {{.*#+}} xmm4 = xmm4[0,0]
+; XOP-NEXT: vinsertf128 $1, %xmm4, %ymm4, %ymm4
+; XOP-NEXT: vpcmpeqd %xmm6, %xmm6, %xmm6
+; XOP-NEXT: vpxor %xmm6, %xmm5, %xmm5
+; XOP-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[0,1,0,1]
+; XOP-NEXT: vinsertf128 $1, %xmm5, %ymm5, %ymm5
+; XOP-NEXT: vandps %ymm4, %ymm1, %ymm1
+; XOP-NEXT: vandps %ymm4, %ymm0, %ymm0
+; XOP-NEXT: vandps %ymm5, %ymm3, %ymm3
+; XOP-NEXT: vorps %ymm3, %ymm1, %ymm1
+; XOP-NEXT: vandps %ymm5, %ymm2, %ymm2
+; XOP-NEXT: vorps %ymm2, %ymm0, %ymm0
+; XOP-NEXT: retq
+;
+; AVX1-LABEL: bitselect_v8i64_broadcast_rrr:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovq %rdi, %xmm4
+; AVX1-NEXT: vmovq %rdi, %xmm5
+; AVX1-NEXT: vmovddup {{.*#+}} xmm4 = xmm4[0,0]
+; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm4, %ymm4
+; AVX1-NEXT: vpcmpeqd %xmm6, %xmm6, %xmm6
+; AVX1-NEXT: vpxor %xmm6, %xmm5, %xmm5
+; AVX1-NEXT: vpshufd {{.*#+}} xmm5 = xmm5[0,1,0,1]
+; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm5, %ymm5
+; AVX1-NEXT: vandps %ymm4, %ymm1, %ymm1
+; AVX1-NEXT: vandps %ymm4, %ymm0, %ymm0
+; AVX1-NEXT: vandps %ymm5, %ymm3, %ymm3
+; AVX1-NEXT: vorps %ymm3, %ymm1, %ymm1
+; AVX1-NEXT: vandps %ymm5, %ymm2, %ymm2
+; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: bitselect_v8i64_broadcast_rrr:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vmovq %rdi, %xmm4
+; AVX2-NEXT: vpbroadcastq %xmm4, %ymm4
+; AVX2-NEXT: vpand %ymm4, %ymm1, %ymm1
+; AVX2-NEXT: vpand %ymm4, %ymm0, %ymm0
+; AVX2-NEXT: vpandn %ymm3, %ymm4, %ymm3
+; AVX2-NEXT: vpor %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vpandn %ymm2, %ymm4, %ymm2
+; AVX2-NEXT: vpor %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: bitselect_v8i64_broadcast_rrr:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpbroadcastq %rdi, %zmm2
+; AVX512-NEXT: vpternlogq $226, %zmm1, %zmm2, %zmm0
+; AVX512-NEXT: retq
+ %1 = insertelement <8 x i64> undef, i64 %a2, i32 0
+ %2 = shufflevector <8 x i64> %1, <8 x i64> undef, <8 x i32> zeroinitializer
+ %3 = xor <8 x i64> %1, <i64 -1, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>
+ %4 = shufflevector <8 x i64> %3, <8 x i64> undef, <8 x i32> zeroinitializer
+ %5 = and <8 x i64> %a0, %2
+ %6 = and <8 x i64> %a1, %4
+ %7 = or <8 x i64> %5, %6
+ ret <8 x i64> %7
+}
+
+define <8 x i64> @bitselect_v8i64_broadcast_rrm(<8 x i64> %a0, <8 x i64> %a1, i64* %p2) {
+; SSE-LABEL: bitselect_v8i64_broadcast_rrm:
+; SSE: # %bb.0:
+; SSE-NEXT: movq {{.*#+}} xmm8 = mem[0],zero
+; SSE-NEXT: pshufd {{.*#+}} xmm9 = xmm8[0,1,0,1]
+; SSE-NEXT: pcmpeqd %xmm10, %xmm10
+; SSE-NEXT: pxor %xmm8, %xmm10
+; SSE-NEXT: pshufd {{.*#+}} xmm8 = xmm10[0,1,0,1]
+; SSE-NEXT: pand %xmm9, %xmm3
+; SSE-NEXT: pand %xmm9, %xmm2
+; SSE-NEXT: pand %xmm9, %xmm1
+; SSE-NEXT: pand %xmm9, %xmm0
+; SSE-NEXT: pand %xmm8, %xmm7
+; SSE-NEXT: por %xmm7, %xmm3
+; SSE-NEXT: pand %xmm8, %xmm6
+; SSE-NEXT: por %xmm6, %xmm2
+; SSE-NEXT: pand %xmm8, %xmm5
+; SSE-NEXT: por %xmm5, %xmm1
+; SSE-NEXT: pand %xmm8, %xmm4
+; SSE-NEXT: por %xmm4, %xmm0
+; SSE-NEXT: retq
+;
+; XOP-LABEL: bitselect_v8i64_broadcast_rrm:
+; XOP: # %bb.0:
+; XOP-NEXT: vmovq {{.*#+}} xmm4 = mem[0],zero
+; XOP-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[0,1,0,1]
+; XOP-NEXT: vinsertf128 $1, %xmm5, %ymm5, %ymm5
+; XOP-NEXT: vpcmpeqd %xmm6, %xmm6, %xmm6
+; XOP-NEXT: vpxor %xmm6, %xmm4, %xmm4
+; XOP-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[0,1,0,1]
+; XOP-NEXT: vinsertf128 $1, %xmm4, %ymm4, %ymm4
+; XOP-NEXT: vandps %ymm5, %ymm1, %ymm1
+; XOP-NEXT: vandps %ymm5, %ymm0, %ymm0
+; XOP-NEXT: vandps %ymm4, %ymm3, %ymm3
+; XOP-NEXT: vorps %ymm3, %ymm1, %ymm1
+; XOP-NEXT: vandps %ymm4, %ymm2, %ymm2
+; XOP-NEXT: vorps %ymm2, %ymm0, %ymm0
+; XOP-NEXT: retq
+;
+; AVX1-LABEL: bitselect_v8i64_broadcast_rrm:
+; AVX1: # %bb.0:
+; AVX1-NEXT: vmovq {{.*#+}} xmm4 = mem[0],zero
+; AVX1-NEXT: vpshufd {{.*#+}} xmm5 = xmm4[0,1,0,1]
+; AVX1-NEXT: vinsertf128 $1, %xmm5, %ymm5, %ymm5
+; AVX1-NEXT: vpcmpeqd %xmm6, %xmm6, %xmm6
+; AVX1-NEXT: vpxor %xmm6, %xmm4, %xmm4
+; AVX1-NEXT: vpshufd {{.*#+}} xmm4 = xmm4[0,1,0,1]
+; AVX1-NEXT: vinsertf128 $1, %xmm4, %ymm4, %ymm4
+; AVX1-NEXT: vandps %ymm5, %ymm1, %ymm1
+; AVX1-NEXT: vandps %ymm5, %ymm0, %ymm0
+; AVX1-NEXT: vandps %ymm4, %ymm3, %ymm3
+; AVX1-NEXT: vorps %ymm3, %ymm1, %ymm1
+; AVX1-NEXT: vandps %ymm4, %ymm2, %ymm2
+; AVX1-NEXT: vorps %ymm2, %ymm0, %ymm0
+; AVX1-NEXT: retq
+;
+; AVX2-LABEL: bitselect_v8i64_broadcast_rrm:
+; AVX2: # %bb.0:
+; AVX2-NEXT: vbroadcastsd (%rdi), %ymm4
+; AVX2-NEXT: vandps %ymm4, %ymm1, %ymm1
+; AVX2-NEXT: vandps %ymm4, %ymm0, %ymm0
+; AVX2-NEXT: vandnps %ymm3, %ymm4, %ymm3
+; AVX2-NEXT: vorps %ymm3, %ymm1, %ymm1
+; AVX2-NEXT: vandnps %ymm2, %ymm4, %ymm2
+; AVX2-NEXT: vorps %ymm2, %ymm0, %ymm0
+; AVX2-NEXT: retq
+;
+; AVX512-LABEL: bitselect_v8i64_broadcast_rrm:
+; AVX512: # %bb.0:
+; AVX512-NEXT: vpternlogq $228, (%rdi){1to8}, %zmm1, %zmm0
+; AVX512-NEXT: retq
+ %a2 = load i64, i64* %p2
+ %1 = insertelement <8 x i64> undef, i64 %a2, i32 0
+ %2 = shufflevector <8 x i64> %1, <8 x i64> undef, <8 x i32> zeroinitializer
+ %3 = xor <8 x i64> %1, <i64 -1, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef, i64 undef>
+ %4 = shufflevector <8 x i64> %3, <8 x i64> undef, <8 x i32> zeroinitializer
+ %5 = and <8 x i64> %a0, %2
+ %6 = and <8 x i64> %a1, %4
+ %7 = or <8 x i64> %5, %6
+ ret <8 x i64> %7
+}
+
; Check that mask registers don't get canonicalized.
define <4 x i1> @bitselect_v4i1_loop(<4 x i32> %a0, <4 x i32> %a1) {
; SSE-LABEL: bitselect_v4i1_loop:
@@ -760,6 +1142,17 @@ define <4 x i1> @bitselect_v4i1_loop(<4 x i32> %a0, <4 x i32> %a1) {
; AVX512F-NEXT: # kill: def $xmm0 killed $xmm0 killed $zmm0
; AVX512F-NEXT: vzeroupper
; AVX512F-NEXT: retq
+;
+; AVX512VL-LABEL: bitselect_v4i1_loop:
+; AVX512VL: # %bb.0: # %bb
+; AVX512VL-NEXT: vpcmpeqd {{.*}}(%rip){1to4}, %xmm1, %k1
+; AVX512VL-NEXT: vpcmpeqd {{.*}}(%rip){1to4}, %xmm1, %k2
+; AVX512VL-NEXT: vptestnmd %xmm0, %xmm0, %k0 {%k2}
+; AVX512VL-NEXT: vptestmd %xmm0, %xmm0, %k1 {%k1}
+; AVX512VL-NEXT: korw %k0, %k1, %k1
+; AVX512VL-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
+; AVX512VL-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z}
+; AVX512VL-NEXT: retq
bb:
%tmp = icmp ne <4 x i32> %a0, zeroinitializer
%tmp2 = icmp eq <4 x i32> %a1, <i32 12, i32 12, i32 12, i32 12>
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