[PATCH] D78908: [RISCV] Add patterns for checking isnan

[Alex Bradbury via Phabricator via llvm-commits]

asb accepted this revision.
asb added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!



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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoD.td:316
                  1)>;
+def : Pat<(setuo FPR64:$rs1, FPR64:$rs1),
+          (SLTIU (FEQ_D $rs1, $rs1), 1)>;
----------------
lenary wrote:
> asb wrote:
> > I think this pattern and the matching one in RISCVInstrInfoF.td is left untested?
> This pattern is what is tested by `fcmp uno {float,double} %0, 0.000000e+00`. The `sltiu` is shown in the assembly output as `seqz`.
Doh - thanks!


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https://reviews.llvm.org/D78908