[llvm] d3dc4c3 - [AArch64] Remove inexistent system register ERXTS_EL1

[Victor Campos via llvm-commits]

Author: Victor Campos
Date: 2020-04-29T16:43:48+01:00
New Revision: d3dc4c32afb4ce8cd311e70ac407d68e2d42742e

URL: https://github.com/llvm/llvm-project/commit/d3dc4c32afb4ce8cd311e70ac407d68e2d42742e
DIFF: https://github.com/llvm/llvm-project/commit/d3dc4c32afb4ce8cd311e70ac407d68e2d42742e.diff

LOG: [AArch64] Remove inexistent system register ERXTS_EL1

Summary:
AArch64's system register ERXTS_EL1 is present in the backend as a
component of the Arm Reliability, Availability and Serviceability (RAS)
extension. However, it has been removed from the specification before
its final release.

This patch removes the register.

Reviewers: SjoerdMeijer, DavidSpickett

Reviewed By: DavidSpickett

Subscribers: DavidSpickett, kristof.beyls, hiraditya, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D79007

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64SystemOperands.td
    llvm/test/MC/AArch64/armv8.4a-ras.s
    llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64SystemOperands.td b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
index 6cb1b6ef391d..ceceabc6ff4e 100644
--- a/llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ b/llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1331,7 +1331,6 @@ def : RWSysReg<"PMMIR_EL1", 0b11, 0b000, 0b1001, 0b1110, 0b110>;
 let Requires = [{ {AArch64::FeatureRASv8_4} }] in {
 def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>;
 def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>;
-def : RWSysReg<"ERXTS_EL1",     0b11, 0b000, 0b0101, 0b0101, 0b111>;
 def : RWSysReg<"ERXMISC2_EL1",  0b11, 0b000, 0b0101, 0b0101, 0b010>;
 def : RWSysReg<"ERXMISC3_EL1",  0b11, 0b000, 0b0101, 0b0101, 0b011>;
 def : ROSysReg<"ERXPFGF_EL1",   0b11, 0b000, 0b0101, 0b0100, 0b100>;

diff  --git a/llvm/test/MC/AArch64/armv8.4a-ras.s b/llvm/test/MC/AArch64/armv8.4a-ras.s
index d89baf7bd7eb..5e96d2711a0b 100644
--- a/llvm/test/MC/AArch64/armv8.4a-ras.s
+++ b/llvm/test/MC/AArch64/armv8.4a-ras.s
@@ -23,14 +23,6 @@
 //CHECK:  msr ERXPFGCDN_EL1, x0       // encoding: [0xc0,0x54,0x18,0xd5]
 //CHECK:  mrs x0, ERXPFGCDN_EL1       // encoding: [0xc0,0x54,0x38,0xd5]
 //CHECK-ERROR: error: expected writable system register or pstate
-//CHECK-ERROR: error: expected readable system register
-
-  msr ERXTS_EL1, x0
-  mrs x0,ERXTS_EL1
-
-//CHECK:  msr ERXTS_EL1, x0           // encoding: [0xe0,0x55,0x18,0xd5]
-//CHECK:  mrs x0, ERXTS_EL1           // encoding: [0xe0,0x55,0x38,0xd5]
-//CHECK-ERROR: error: expected writable system register or pstate
 //CHECK-ERROR: error: expected readable system register
 
   msr ERXMISC2_EL1, x0

diff  --git a/llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt b/llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt
index ef38b71fb9e0..afae16dc1438 100644
--- a/llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt
+++ b/llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt
@@ -4,8 +4,6 @@
 0xa0,0x54,0x38,0xd5
 0xc0,0x54,0x18,0xd5
 0xc0,0x54,0x38,0xd5
-0xe0,0x55,0x18,0xd5
-0xe0,0x55,0x38,0xd5
 0x80,0x54,0x38,0xd5
 
 0x40,0x55,0x18,0xd5
@@ -17,8 +15,6 @@
 #CHECK:  mrs x0, ERXPFGCTL_EL1
 #CHECK:  msr ERXPFGCDN_EL1, x0
 #CHECK:  mrs x0, ERXPFGCDN_EL1
-#CHECK:  msr ERXTS_EL1, x0
-#CHECK:  mrs x0, ERXTS_EL1
 #CHECK:  mrs x0, ERXPFGF_EL1
 
 #CHECK:  msr ERXMISC2_EL1, x0