[llvm] c480dc6 - [X86] Pre-commit tests for D78984. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2020-04-28T10:39:37-07:00
New Revision: c480dc6b47cf29b2a14c14a5544d153de091644e

URL: https://github.com/llvm/llvm-project/commit/c480dc6b47cf29b2a14c14a5544d153de091644e
DIFF: https://github.com/llvm/llvm-project/commit/c480dc6b47cf29b2a14c14a5544d153de091644e.diff

LOG: [X86] Pre-commit tests for D78984. NFC

These tests show some missed opportunities to use sbb/adc.

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/sbb.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/X86/sbb.ll b/llvm/test/CodeGen/X86/sbb.ll
index cc8127cbea23..fc7d9bacab79 100644
--- a/llvm/test/CodeGen/X86/sbb.ll
+++ b/llvm/test/CodeGen/X86/sbb.ll
@@ -245,3 +245,113 @@ end:
   ret void
 }
 
+; Cases for PR45700
+define i32 @ult_zext_add(i32 %0, i32 %1, i32 %2) {
+; CHECK-LABEL: ult_zext_add:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    cmpl %edx, %esi
+; CHECK-NEXT:    adcl $0, %eax
+; CHECK-NEXT:    retq
+  %4 = icmp ult i32 %1, %2
+  %5 = zext i1 %4 to i32
+  %6 = add nsw i32 %5, %0
+  ret i32 %6
+}
+
+define i32 @ule_zext_add(i32 %0, i32 %1, i32 %2) {
+; CHECK-LABEL: ule_zext_add:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    cmpl %edx, %esi
+; CHECK-NEXT:    setbe %al
+; CHECK-NEXT:    addl %edi, %eax
+; CHECK-NEXT:    retq
+  %4 = icmp ule i32 %1, %2
+  %5 = zext i1 %4 to i32
+  %6 = add nsw i32 %5, %0
+  ret i32 %6
+}
+
+define i32 @ugt_zext_add(i32 %0, i32 %1, i32 %2) {
+; CHECK-LABEL: ugt_zext_add:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    cmpl %esi, %edx
+; CHECK-NEXT:    adcl $0, %eax
+; CHECK-NEXT:    retq
+  %4 = icmp ugt i32 %1, %2
+  %5 = zext i1 %4 to i32
+  %6 = add nsw i32 %5, %0
+  ret i32 %6
+}
+
+define i32 @uge_zext_add(i32 %0, i32 %1, i32 %2) {
+; CHECK-LABEL: uge_zext_add:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    xorl %eax, %eax
+; CHECK-NEXT:    cmpl %edx, %esi
+; CHECK-NEXT:    setae %al
+; CHECK-NEXT:    addl %edi, %eax
+; CHECK-NEXT:    retq
+  %4 = icmp uge i32 %1, %2
+  %5 = zext i1 %4 to i32
+  %6 = add nsw i32 %5, %0
+  ret i32 %6
+}
+
+define i32 @ult_sext_add(i32 %0, i32 %1, i32 %2) {
+; CHECK-LABEL: ult_sext_add:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    cmpl %edx, %esi
+; CHECK-NEXT:    sbbl $0, %eax
+; CHECK-NEXT:    retq
+  %4 = icmp ult i32 %1, %2
+  %5 = sext i1 %4 to i32
+  %6 = add nsw i32 %5, %0
+  ret i32 %6
+}
+
+define i32 @ule_sext_add(i32 %0, i32 %1, i32 %2) {
+; CHECK-LABEL: ule_sext_add:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    cmpl %edx, %esi
+; CHECK-NEXT:    setbe %cl
+; CHECK-NEXT:    subl %ecx, %eax
+; CHECK-NEXT:    retq
+  %4 = icmp ule i32 %1, %2
+  %5 = sext i1 %4 to i32
+  %6 = add nsw i32 %5, %0
+  ret i32 %6
+}
+
+define i32 @ugt_sext_add(i32 %0, i32 %1, i32 %2) {
+; CHECK-LABEL: ugt_sext_add:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    cmpl %esi, %edx
+; CHECK-NEXT:    sbbl $0, %eax
+; CHECK-NEXT:    retq
+  %4 = icmp ugt i32 %1, %2
+  %5 = sext i1 %4 to i32
+  %6 = add nsw i32 %5, %0
+  ret i32 %6
+}
+
+define i32 @uge_sext_add(i32 %0, i32 %1, i32 %2) {
+; CHECK-LABEL: uge_sext_add:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    xorl %ecx, %ecx
+; CHECK-NEXT:    cmpl %edx, %esi
+; CHECK-NEXT:    setae %cl
+; CHECK-NEXT:    subl %ecx, %eax
+; CHECK-NEXT:    retq
+  %4 = icmp uge i32 %1, %2
+  %5 = sext i1 %4 to i32
+  %6 = add nsw i32 %5, %0
+  ret i32 %6
+}