[PATCH] D79007: [AArch64] Remove inexistent system register ERXTS_EL1

[Victor Campos via Phabricator via llvm-commits]

vhscampos created this revision.
Herald added subscribers: llvm-commits, danielkiss, hiraditya, kristof.beyls.
Herald added a project: LLVM.
vhscampos added a reviewer: SjoerdMeijer.
DavidSpickett accepted this revision.
DavidSpickett added a comment.
This revision is now accepted and ready to land.

LGTM, no sign of it in the current armarm.


AArch64's system register ERXTS_EL1 is present in the backend as a
component of the Arm Reliability, Availability and Serviceability (RAS)
extension. However, it has been removed from the specification before
its final release.

This patch removes the register.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D79007

Files:
  llvm/lib/Target/AArch64/AArch64SystemOperands.td
  llvm/test/MC/AArch64/armv8.4a-ras.s
  llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt


Index: llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt
===================================================================
--- llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt
+++ llvm/test/MC/Disassembler/AArch64/armv8.4a-ras.txt
@@ -4,8 +4,6 @@
 0xa0,0x54,0x38,0xd5
 0xc0,0x54,0x18,0xd5
 0xc0,0x54,0x38,0xd5
-0xe0,0x55,0x18,0xd5
-0xe0,0x55,0x38,0xd5
 0x80,0x54,0x38,0xd5
 
 0x40,0x55,0x18,0xd5
@@ -17,8 +15,6 @@
 #CHECK:  mrs x0, ERXPFGCTL_EL1
 #CHECK:  msr ERXPFGCDN_EL1, x0
 #CHECK:  mrs x0, ERXPFGCDN_EL1
-#CHECK:  msr ERXTS_EL1, x0
-#CHECK:  mrs x0, ERXTS_EL1
 #CHECK:  mrs x0, ERXPFGF_EL1
 
 #CHECK:  msr ERXMISC2_EL1, x0
Index: llvm/test/MC/AArch64/armv8.4a-ras.s
===================================================================
--- llvm/test/MC/AArch64/armv8.4a-ras.s
+++ llvm/test/MC/AArch64/armv8.4a-ras.s
@@ -23,14 +23,6 @@
 //CHECK:  msr ERXPFGCDN_EL1, x0       // encoding: [0xc0,0x54,0x18,0xd5]
 //CHECK:  mrs x0, ERXPFGCDN_EL1       // encoding: [0xc0,0x54,0x38,0xd5]
 //CHECK-ERROR: error: expected writable system register or pstate
-//CHECK-ERROR: error: expected readable system register
-
-  msr ERXTS_EL1, x0
-  mrs x0,ERXTS_EL1
-
-//CHECK:  msr ERXTS_EL1, x0           // encoding: [0xe0,0x55,0x18,0xd5]
-//CHECK:  mrs x0, ERXTS_EL1           // encoding: [0xe0,0x55,0x38,0xd5]
-//CHECK-ERROR: error: expected writable system register or pstate
 //CHECK-ERROR: error: expected readable system register
 
   msr ERXMISC2_EL1, x0
Index: llvm/lib/Target/AArch64/AArch64SystemOperands.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64SystemOperands.td
+++ llvm/lib/Target/AArch64/AArch64SystemOperands.td
@@ -1331,7 +1331,6 @@
 let Requires = [{ {AArch64::FeatureRASv8_4} }] in {
 def : RWSysReg<"ERXPFGCTL_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b101>;
 def : RWSysReg<"ERXPFGCDN_EL1", 0b11, 0b000, 0b0101, 0b0100, 0b110>;
-def : RWSysReg<"ERXTS_EL1",     0b11, 0b000, 0b0101, 0b0101, 0b111>;
 def : RWSysReg<"ERXMISC2_EL1",  0b11, 0b000, 0b0101, 0b0101, 0b010>;
 def : RWSysReg<"ERXMISC3_EL1",  0b11, 0b000, 0b0101, 0b0101, 0b011>;
 def : ROSysReg<"ERXPFGF_EL1",   0b11, 0b000, 0b0101, 0b0100, 0b100>;


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