[PATCH] D78010: [CodeGen] Add new function unionImplicitOps() to union implicit register

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/PowerPC/PPCEarlyReturn.cpp:80-81
               // branch with a blr.
               BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode()))
-                  .copyImplicitOps(*I);
+                  .unionImplicitOps(*I);
               MachineBasicBlock::iterator K = J--;
----------------
Do you just want to setDesc here instead? It seems to me you expect the same implicit operands before and after in the test, and just want to change the opcode


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78010/new/

https://reviews.llvm.org/D78010