[PATCH] D78998: [MIPS] Add a baseline test showing current inefficient hidden sret lowering

Alexander Richardson via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Apr 28 06:24:17 PDT 2020


arichardson created this revision.
Herald added subscribers: llvm-commits, atanasyan, jrtc27, sdardis.
Herald added a project: LLVM.
arichardson added a child revision: D78999: [SelectionDAGBuilder] Stop setting alignment to one for hidden sret values.
arichardson requested review of this revision.

This is inefficient for MIPS and highly inefficient for CHERI since we
don't have lwl/lwr so fall back to byte loads for align == 1.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78998

Files:
  llvm/test/CodeGen/Mips/implicit-sret.ll

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