[PATCH] D78986: [PowerPC-QPX] adjust operands order of qpx vector fma instructions.

[ChenZheng via Phabricator via llvm-commits]

shchenz created this revision.
shchenz added reviewers: hfinkel, PowerPC.
Herald added subscribers: llvm-commits, wuzish, kbarton, hiraditya, nemanjai.
Herald added a project: LLVM.

Now after isel, operand order for qpx vector fma instruction `qvfmadd` is like:

  %3 = QVFMADD %2, %0, %1, implicit $rm

This stands for `%3 = %2 * %1 + %0`. This is a little different with QPX ISA's description and also not same with other Power arch vector fma instrucions, like `xvmaddadp`

It should be like `%3 = QVFMADD %2, %1, %0, implicit $rm`


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78986

Files:
  llvm/lib/Target/PowerPC/PPCInstrQPX.td
  llvm/test/CodeGen/PowerPC/qpx-qvfmadd.ll


Index: llvm/test/CodeGen/PowerPC/qpx-qvfmadd.ll
===================================================================
--- llvm/test/CodeGen/PowerPC/qpx-qvfmadd.ll
+++ llvm/test/CodeGen/PowerPC/qpx-qvfmadd.ll
@@ -2,7 +2,7 @@
 
 define <2 x double> @test_qvfmadd(<2 x double> %0, <2 x double> %1, <2 x double> %2) {
 ; CHECK: test_qvfmadd
-; CHECK: QVFMADD %2, %0, %1, implicit $rm
+; CHECK: QVFMADD %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <2 x double> %2, %1
   %5 = fadd reassoc nsz <2 x double> %4, %0
@@ -11,7 +11,7 @@
 
 define <4 x float> @test_qvfmadds(<4 x float> %0, <4 x float> %1, <4 x float> %2) {
 ; CHECK: test_qvfmadds
-; CHECK: QVFMADDSs %2, %0, %1, implicit $rm
+; CHECK: QVFMADDSs %2, %1, %0, implicit $rm
 ;
   %4 = fmul reassoc nsz <4 x float> %2, %1
   %5 = fadd reassoc nsz <4 x float> %4, %0
Index: llvm/lib/Target/PowerPC/PPCInstrQPX.td
===================================================================
--- llvm/lib/Target/PowerPC/PPCInstrQPX.td
+++ llvm/lib/Target/PowerPC/PPCInstrQPX.td
@@ -167,13 +167,13 @@
 
   // Multiply-add instructions
   def QVFMADD : AForm_1<4, 29,
-                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRB, qfrc:$FRC),
+                      (outs qfrc:$FRT), (ins qfrc:$FRA, qfrc:$FRC, qfrc:$FRB),
                       "qvfmadd $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                       [(set v4f64:$FRT, (fma v4f64:$FRA, v4f64:$FRC, v4f64:$FRB))]>;
   let isCodeGenOnly = 1 in
     def QVFMADDS : QPXA1_Int<0, 29, "qvfmadds", int_ppc_qpx_qvfmadds>;
   def QVFMADDSs : AForm_1<0, 29,
-                        (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRB, qsrc:$FRC),
+                        (outs qsrc:$FRT), (ins qsrc:$FRA, qsrc:$FRC, qsrc:$FRB),
                         "qvfmadds $FRT, $FRA, $FRC, $FRB", IIC_FPFused,
                         [(set v4f32:$FRT, (fma v4f32:$FRA, v4f32:$FRC, v4f32:$FRB))]>;
   def QVFNMADD : AForm_1<4, 31,


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