[PATCH] D78772: [AMDGPU] Adapt GCNRegBankReassign for 16 bit subregs

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec updated this revision to Diff 260418.
rampitec marked an inline comment as done.
rampitec added a comment.
Herald added a project: LLVM.

- Scan applicable RC with getMatchingSuperReg in get32BitRegister().
- Removed divideCell from getChannelFromSubReg() to simplify it.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78772/new/

https://reviews.llvm.org/D78772

Files:
  llvm/lib/Target/AMDGPU/GCNRegBankReassign.cpp
  llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.h
  llvm/test/CodeGen/AMDGPU/regbank-reassign.mir

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D78772.260418.patch
Type: text/x-patch
Size: 8482 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200427/db515b83/attachment.bin>