[PATCH] D78910: [RISCV] RISCBoy Scheduling Model

[Sam Elliott via Phabricator via llvm-commits]

lenary created this revision.
Herald added subscribers: llvm-commits, evandro, luismarques, apazos, sameer.abuasal, pzheng, s.egerton, Jim, benna, psnobl, jocewei, PkmX, jfb, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, asb, hiraditya.
Herald added a project: LLVM.

As a way to learn how to write a Scheduling Model for RISC-V cores, I decided to
see if I could write one for a well-documented open-source core.

I'm not sure if I have all the information in the model correct yet, in
particular I know RISCBoy has some forwarding that I don't think I've modelled,
and I probably missed how to correctly model a five-stage in-order pipeline.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78910

Files:
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSchedRISCBoy.td

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D78910.260258.patch
Type: text/x-patch
Size: 8942 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200427/876949ff/attachment.bin>