[PATCH] D78906: [RISCV] Add patterns for indirect float conversions

[Sam Elliott via Phabricator via llvm-commits]

lenary marked an inline comment as done.
lenary added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoF.td:397-404
-let Predicates = [HasStdExtF, IsRV32] in {
-// FP->[u]int. Round-to-zero must be used
-def : Pat<(fp_to_sint FPR32:$rs1), (FCVT_W_S $rs1, 0b001)>;
-def : Pat<(fp_to_uint FPR32:$rs1), (FCVT_WU_S $rs1, 0b001)>;
 
-// [u]int->fp. Match GCC and default to using dynamic rounding mode.
-def : Pat<(sint_to_fp GPR:$rs1), (FCVT_S_W $rs1, 0b111)>;
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These patterns were duplicated in this file, which seems incorrect.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78906/new/

https://reviews.llvm.org/D78906