[PATCH] D78889: [VE] Update branch instructions

[Kazushi Marukawa via Phabricator via llvm-commits]

kaz7 marked 4 inline comments as done.
kaz7 added inline comments.


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Comment at: llvm/lib/Target/VE/VEInstrInfo.cpp:28
 
-#define DEBUG_TYPE "ve"
+#define DEBUG_TYPE "ve-instr-info"
 
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simoll wrote:
> unrelated change
Reverted it.


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Comment at: llvm/lib/Target/VE/VEInstrInfo.cpp:206
     assert(!FBB && "Unconditional branch with multiple successors!");
-    BuildMI(&MBB, DL, get(VE::BCRLa))
-        .addMBB(TBB);
+    BuildMI(&MBB, DL, get(VE::BRCFLa_t)).addMBB(TBB);
     return 1;
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simoll wrote:
> Formatting. Please put the `addMBB` on the next line to follow the style of the code.
Clang format modified it as this.  I reverted it.  Thanks.


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Comment at: llvm/lib/Target/VE/VEInstrInfo.cpp:253
 
-  BuildMI(&MBB, DL, get(VE::BCRLa))
-      .addMBB(FBB);
+  BuildMI(&MBB, DL, get(VE::BRCFLa_t)).addMBB(FBB);
   return 2;
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simoll wrote:
> same
same


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Comment at: llvm/lib/Target/VE/VEInstrInfo.td:1131
+def CALLr : RM<0x08, (outs), (ins I64:$sz, variable_ops),
+               "bsic %s10, (, $sz)", [(call i64:$sz)]>;
 
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simoll wrote:
> In the tests below `%lr` has turned into `%s10` . I suppose you could replace the asm string `bsic %s10` here with `bsic %lr` to prevent this (at least for this pattern).
I modified them to use `%s10` register consistently.  I'll write it in the summary later.  Thank you for the suggestion.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D78889/new/

https://reviews.llvm.org/D78889