[PATCH] D78811: [AMDGPU] Enable base pointer.

[Christudasan Devadasan via Phabricator via llvm-commits]

cdevadas marked 2 inline comments as done.
cdevadas added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIFrameLowering.cpp:885
+  if (FuncInfo->BasePointerSaveIndex) {
+    const int BasePtrFI = FuncInfo->BasePointerSaveIndex.getValue();
+
----------------
arsenm wrote:
> * BasePointerSaveIndex is probably the normal way to get the value
Here getValue() is required. It is of type Optional<int>.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:122
+
+Register SIRegisterInfo::getBaseRegister() const { return AMDGPU::SGPR34; }
+
----------------
arsenm wrote:
> Can this go in the header or is is the register enum not defined there?
Right, the enum isn't defined there. 


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D78811/new/

https://reviews.llvm.org/D78811