[PATCH] D76158: Add inline assembly load hardening mitigation for Load Value Injection (LVI) on X86 [6/6]

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3186
+  switch (Inst.getOpcode()) {
+  case X86::RET:
+  case X86::RETL:
----------------
RET is a pseudo. It will never be parsed.
RETW is missing.
LRETL, LRETW, LRETQ, LRETIL, LRETIW, LRETIQ are missing based on what binutils does.


================
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3195
+  case X86::JMP64m:
+  case X86::JMP64m_REX:
+  case X86::FARJMP16m:
----------------
JMP64m_REX is a special codegen pseudo instruction. It won't be parsed.


================
Comment at: llvm/lib/Target/X86/AsmParser/X86AsmParser.cpp:3196
+  case X86::JMP64m_REX:
+  case X86::FARJMP16m:
+  case X86::FARJMP32m:
----------------
binutils does not handle the FARJMP/FARCALL. Is that a miss or them or something else?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76158/new/

https://reviews.llvm.org/D76158