[PATCH] D78772: [AMDGPU] Adapt GCNRegBankReassign for 16 bit subregs

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp:1789-1790
+  const TargetRegisterClass *RC = getPhysRegClass(Reg);
+  if (getRegSizeInBits(*RC) != 16)
+    return Reg;
+
----------------
rampitec wrote:
> arsenm wrote:
> > Seems like this should just be an assert
> I am going to use it without checking is a register actually 16 or 32 bit, just to get a 32 bit operand from whatever input. But it is reasonable to add assert for "Size <= 32".
I think you can get away with looking up the specific register class, and picking the right 32-bit class by just trying VGPR,SGPR,AGPR in succession and see if any succeed


================
Comment at: llvm/lib/Target/AMDGPU/SIRegisterInfo.h:287-288
   unsigned getChannelFromSubReg(unsigned SubReg) const {
-    return SubReg ? divideCeil(getSubRegIdxOffset(SubReg), 32) : 0;
+    if (!SubReg)
+      return 0;
+    unsigned Offset = getSubRegIdxOffset(SubReg) & ~31u;
----------------
I would expect this to be an assert, but. guess it already handled this case


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  https://reviews.llvm.org/D78772/new/

https://reviews.llvm.org/D78772