[PATCH] D78318: [GlobalISel][InlineAsm] Add support for basic output operand constraints

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp:693-694
       // regclasses.
-      if (isTargetSpecificOpcode(MI.getOpcode()) && !MI.isPreISelOpcode())
+      if ((isTargetSpecificOpcode(MI.getOpcode()) && !MI.isPreISelOpcode()) ||
+          MI.isInlineAsm())
         continue;
----------------
kschwarz wrote:
> kschwarz wrote:
> > arsenm wrote:
> > > This part isn't tested, I would leave this for a separate patch. I'm not sure checking for inline asm explicitly is the right thing here
> > Sure I can remove this change from the patch. I temporarily removed the -stop-after argument from the irtranslator test to run down to assembly, which resulted in a crash in the register bank selector of AArch64.
> > Since we cannot have generic virtual registers on INLINEASM instructions, I figured not trying to select a register bank for these instructions would be fine.
> After removing this line, another AArch64 test starts failing (stack_guard_remat.ll). It triggers the very same crash in the register bank selector of AArch64: llvm::LLT::getScalarSizeInBits() const: Assertion 'RawData != 0 && "Invalid Type"'.
> 
> What do you think would be an appropriate check during register bank selection?
OK, can you add an explicit regbankselect for asm test then?



Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78318/new/

https://reviews.llvm.org/D78318