[PATCH] D78812: [SVE][CodeGen] Fix legalisation for scalable types

Eli Friedman via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Fri Apr 24 13:33:26 PDT 2020


efriedma added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp:738
+      *DAG.getContext(), IntermediateVT.getScalarType(), DestVectorNoElts,
+      ValueVT.isScalableVector());
   if (ValueVT != BuiltVectorTy) {
----------------
Can we use ElementCount here?


================
Comment at: llvm/lib/CodeGen/TargetLoweringBase.cpp:1429
+  while (NumElts > 1 &&
+         !isTypeLegal(EVT::getVectorVT(Context, EltTy, NumElts, IsScalable))) {
     NumElts >>= 1;
----------------
Can we use ElementCount here?


================
Comment at: llvm/test/CodeGen/AArch64/llvm-ir-to-intrinsic.ll:107
+  ret <vscale x 4 x i64> %div
+}
----------------
Maybe also worth adding a testcase for `<vscale x 1 x i64>`, assuming that doesn't expose anything really tricky.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78812/new/

https://reviews.llvm.org/D78812





More information about the llvm-commits mailing list