[llvm] 79702dd - [RISCV] Add instruction definition for dret

[Pengxuan Zheng via llvm-commits]

Author: Pengxuan Zheng
Date: 2020-04-24T13:27:43-07:00
New Revision: 79702dd349f31c0c67bf35f36435fdc843fcd052

URL: https://github.com/llvm/llvm-project/commit/79702dd349f31c0c67bf35f36435fdc843fcd052
DIFF: https://github.com/llvm/llvm-project/commit/79702dd349f31c0c67bf35f36435fdc843fcd052.diff

LOG: [RISCV] Add instruction definition for dret

Summary:
The instruction dret is used to return from debug mode and is defined in the
RISC-V debug mode spec.

https://github.com/riscv/riscv-opcodes/blob/master/opcodes-system

Reviewers: apazos, asb, lenary, luismarques

Reviewed By: apazos

Subscribers: jfb, hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, jrtc27, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, PkmX, jocewei, psnobl, benna, Jim, s.egerton, sameer.abuasal, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78583

Added: 
    llvm/test/MC/RISCV/debug-valid.s

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfo.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 28b175a88ad3..1f75dd184cf0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -588,6 +588,18 @@ def SFENCE_VMA : RVInstR<0b0001001, 0b000, OPC_SYSTEM, (outs),
   let rd = 0;
 }
 
+//===----------------------------------------------------------------------===//
+// Debug instructions
+//===----------------------------------------------------------------------===//
+
+let isBarrier = 1, isReturn = 1, isTerminator = 1 in {
+def DRET : Priv<"dret", 0b0111101>, Sched<[]> {
+  let rd = 0;
+  let rs1 = 0;
+  let rs2 = 0b10010;
+}
+} // isBarrier = 1, isReturn = 1, isTerminator = 1
+
 //===----------------------------------------------------------------------===//
 // Assembler Pseudo Instructions (User-Level ISA, Version 2.2, Chapter 20)
 //===----------------------------------------------------------------------===//

diff  --git a/llvm/test/MC/RISCV/debug-valid.s b/llvm/test/MC/RISCV/debug-valid.s
new file mode 100644
index 000000000000..89b8f001b2ce
--- /dev/null
+++ b/llvm/test/MC/RISCV/debug-valid.s
@@ -0,0 +1,14 @@
+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN:     | FileCheck -check-prefixes=CHECK,CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
+# RUN:     | llvm-objdump -M no-aliases -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
+# RUN:     | llvm-objdump -M no-aliases -d - \
+# RUN:     | FileCheck -check-prefix=CHECK-INST %s
+
+# CHECK-INST: dret
+# CHECK: encoding: [0x73,0x00,0x20,0x7b]
+dret