[llvm] cc45767 - [AArch64][FIX] FPR16_lo for f16 indexed patterns.
Eli Friedman via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 24 12:04:35 PDT 2020
There are ways to force register pressure in a small regression test, like inline asm clobbers.
This should have come up in pre-commit code review (which a functional change like this should have gone through)
-Eli
-----Original Message-----
From: Pavel Iliin <Pavel.Iliin at arm.com>
Sent: Friday, April 24, 2020 8:49 AM
To: Eli Friedman <efriedma at quicinc.com>
Subject: [EXT] RE: [llvm] cc45767 - [AArch64][FIX] FPR16_lo for f16 indexed patterns.
Hi Eli!
To test this and allocate hi part (V16-V31 registers) large code ( probably generated one ) with high register pressure required.
I think it could be tested by large applications or/and by generated stress tests, couldn't it?
Thanks for pointing out,
Pavel
-----Original Message-----
From: Eli Friedman <efriedma at quicinc.com>
Sent: 24 April 2020 00:57
To: Pavel Iliin <Pavel.Iliin at arm.com>; llvm-commits <llvm-commits at lists.llvm.org>
Subject: RE: [llvm] cc45767 - [AArch64][FIX] FPR16_lo for f16 indexed patterns.
Missing testcase?
-Eli
-----Original Message-----
From: llvm-commits <llvm-commits-bounces at lists.llvm.org> On Behalf Of Pavel Iliin via llvm-commits
Sent: Thursday, April 23, 2020 3:47 PM
To: llvm-commits at lists.llvm.org
Subject: [EXT] [llvm] cc45767 - [AArch64][FIX] FPR16_lo for f16 indexed patterns.
Author: Pavel Iliin
Date: 2020-04-23T23:44:56+01:00
New Revision: cc457672e628846c20e92c6e0a82896f0d6db031
URL: https://github.com/llvm/llvm-project/commit/cc457672e628846c20e92c6e0a82896f0d6db031
DIFF: https://github.com/llvm/llvm-project/commit/cc457672e628846c20e92c6e0a82896f0d6db031.diff
LOG: [AArch64][FIX] FPR16_lo for f16 indexed patterns.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
llvm/lib/Target/AArch64/AArch64RegisterInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 13f086ff1f5d..1743b0c68eb7 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -8073,9 +8073,9 @@ multiclass SIMDFPIndexedTiedPatterns<string INST, SDPatternOperator OpNode> {
(!cast<Instruction>(INST # "v8i16_indexed")
V128:$Rd, V128:$Rn, V128_lo:$Rm, VectorIndexH:$idx)>;
def : Pat<(v8f16 (OpNode (v8f16 V128:$Rd), (v8f16 V128:$Rn),
- (AArch64dup (f16 FPR16Op:$Rm)))),
+ (AArch64dup (f16 FPR16Op_lo:$Rm)))),
(!cast<Instruction>(INST # "v8i16_indexed") V128:$Rd, V128:$Rn,
- (SUBREG_TO_REG (i32 0), FPR16Op:$Rm, hsub), (i64 0))>;
+ (SUBREG_TO_REG (i32 0), FPR16Op_lo:$Rm, hsub), (i64
+ 0))>;
def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn),
(AArch64duplane16 (v8f16 V128_lo:$Rm), @@ -8083,9 +8083,9 @@ multiclass SIMDFPIndexedTiedPatterns<string INST, SDPatternOperator OpNode> {
(!cast<Instruction>(INST # "v4i16_indexed")
V64:$Rd, V64:$Rn, V128_lo:$Rm, VectorIndexH:$idx)>;
def : Pat<(v4f16 (OpNode (v4f16 V64:$Rd), (v4f16 V64:$Rn),
- (AArch64dup (f16 FPR16Op:$Rm)))),
+ (AArch64dup (f16 FPR16Op_lo:$Rm)))),
(!cast<Instruction>(INST # "v4i16_indexed") V64:$Rd, V64:$Rn,
- (SUBREG_TO_REG (i32 0), FPR16Op:$Rm, hsub), (i64 0))>;
+ (SUBREG_TO_REG (i32 0), FPR16Op_lo:$Rm, hsub), (i64
+ 0))>;
def : Pat<(f16 (OpNode (f16 FPR16:$Rd), (f16 FPR16:$Rn),
(vector_extract (v8f16 V128_lo:$Rm), VectorIndexH:$idx))),
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
index e671ff216214..779986500430 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterBankInfo.cpp
@@ -231,6 +231,8 @@ AArch64RegisterBankInfo::getRegBankFromRegClass(const TargetRegisterClass &RC,
switch (RC.getID()) {
case AArch64::FPR8RegClassID:
case AArch64::FPR16RegClassID:
+ case AArch64::FPR16_loRegClassID:
+ case AArch64::FPR32_with_hsub_in_FPR16_loRegClassID:
case AArch64::FPR32RegClassID:
case AArch64::FPR64RegClassID:
case AArch64::FPR64_loRegClassID:
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index c8556c211957..6c49542e4ff0 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -597,6 +597,7 @@ unsigned AArch64RegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
case AArch64::FPR128_loRegClassID:
case AArch64::FPR64_loRegClassID:
+ case AArch64::FPR16_loRegClassID:
return 16;
}
}
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
index 4cd01234a6ba..93b6aa0cdb7f 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -425,6 +425,9 @@ def FPR8 : RegisterClass<"AArch64", [untyped], 8, (sequence "B%u", 0, 31)> { def FPR16 : RegisterClass<"AArch64", [f16], 16, (sequence "H%u", 0, 31)> {
let Size = 16;
}
+def FPR16_lo : RegisterClass<"AArch64", [f16], 16, (trunc FPR16, 16)> {
+ let Size = 16;
+}
def FPR32 : RegisterClass<"AArch64", [f32, i32], 32,(sequence "S%u", 0, 31)>; def FPR64 : RegisterClass<"AArch64", [f64, i64, v2f32, v1f64, v8i8, v4i16, v2i32,
v1i64, v4f16], @@ -648,6 +651,10 @@ def FPR16Op : RegisterOperand<FPR16, "printOperand"> {
let ParserMatchClass = FPRAsmOperand<"FPR16">; }
+def FPR16Op_lo : RegisterOperand<FPR16_lo, "printOperand"> {
+ let ParserMatchClass = FPRAsmOperand<"FPR16_lo">; }
+
def FPR32Op : RegisterOperand<FPR32, "printOperand"> {
let ParserMatchClass = FPRAsmOperand<"FPR32">; } @@ -671,11 +678,11 @@ def XSeqPairs : RegisterTuples<[sube64, subo64],
[(decimate (rotl GPR64, 0), 2),
(decimate (rotl GPR64, 1), 2)]>;
-def WSeqPairsClass : RegisterClass<"AArch64", [untyped], 32,
+def WSeqPairsClass : RegisterClass<"AArch64", [untyped], 32,
(add WSeqPairs)>{
let Size = 64;
}
-def XSeqPairsClass : RegisterClass<"AArch64", [untyped], 64,
+def XSeqPairsClass : RegisterClass<"AArch64", [untyped], 64,
(add XSeqPairs)>{
let Size = 128;
}
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