[PATCH] D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added a comment.

I think the code is fine now except couple formatting comments.
What is missing specific selection tests.



================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:3688
+    Register CarryReg = MRI.createVirtualRegister(CarryRC);
+    Register DeadCarryReg = MRI.createVirtualRegister(CarryRC);
+
----------------
alex-t wrote:
> rampitec wrote:
> > You can probably use SIInstrInfo::getAddNoCarry() and extend it to produce sub as well or create e new helper. You are always using I32 version even if a no-carry U32 version is available.
> Not sure which line this comment belong...
> For LoOpc I indeed need carry out opcode.
> getAddNoCarry returnc the addition that does not write the carry flag.
> 
> Anyway, the exact opcode is selected later on by the SIInstrInfo::pseudoToMCOpcode
> 
> ```
>   renamable $vgpr0 = V_ADD_I32_e32 1450743926, killed $vgpr0, implicit-def $vcc, implicit $exec
>   renamable $vgpr1 = V_MOV_B32_e32 4660, implicit $exec
>   renamable $vgpr1 = V_ADDC_U32_e32 0, killed $vgpr1, implicit-def $vcc, implicit killed $vcc, implicit $exec
> ```
>  turns to the 
>  
> ```
> 	v_add_co_u32_e32 v0, vcc, 0x56789876, v0
> 	v_mov_b32_e32 v1, 0x1234
> 	v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
> 
> ```
> for gfx9
> 
> but to the
> 
> ```
> 	v_add_i32_e32 v0, vcc, 0x56789876, v0
> 	v_mov_b32_e32 v1, 0x1234
> 	v_addc_u32_e32 v1, vcc, 0, v1, vcc
> 
> ```
> for gfx6
> 
Right, that is add which has these forms. If you need addc you have a dead carry out. So this is OK.


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https://reviews.llvm.org/D78091