[PATCH] D72365: [MTE] Pin the tagged base pointer to one of the stack slots.

[Branislav Rankov via Phabricator via llvm-commits]

rankov added inline comments.


================
Comment at: llvm/lib/Target/AArch64/AArch64StackTaggingPreRA.cpp:256
+  //   instructions count.
+  // - Any other instruction may benefit from being pinned to offset 0.
+  LLVM_DEBUG(dbgs() << "AArch64StackTaggingPreRA::findFirstSlotCandidate\n");
----------------
Size of the slot might be important because of the range of addg. It can only reach 2^6 tag granules (64 * 16B) from base register. If you select a large slot it will reduce the number of slots that can be reached with addg and will result in additional add instructions.

Also, it might be beneficial to sort smaller slots near the SP.


================
Comment at: llvm/test/CodeGen/AArch64/irg_sp_tagp.ll:53
 ; Realigned stack frame. IRG uses value of SP after realignment,
 ; ADDG for the first stack allocation has offset 0.
 define void @realign() {
----------------
There is no addg anymore.


================
Comment at: llvm/test/CodeGen/AArch64/irg_sp_tagp.ll:60
+; CHECK:      irg  x0, sp{{$}}
 ; CHECK:      bl use
   %a = alloca i8, i64 4096, align 64
----------------
Why not check that there is no more addg?


================
Comment at: llvm/test/CodeGen/AArch64/irg_sp_tagp.ll:69
 ; With a dynamic alloca, IRG has to use FP with non-zero offset.
 ; ADDG offset for the single static alloca is still zero.
 define void @dynamic_alloca(i64 %size) {
----------------
No more addg.


================
Comment at: llvm/test/CodeGen/AArch64/irg_sp_tagp.ll:73
 ; CHECK-LABEL: dynamic_alloca:
-; CHECK:      sub  [[R:x[0-9]+]], x29, #[[OFS:[0-9]+]]
-; CHECK:      irg  [[R]], [[R]]
-; CHECK:      addg x1, [[R]], #0, #1
-; CHECK:      sub  x0, x29, #[[OFS]]
+; CHECK:      sub  x1, x29, #[[OFS:[0-9]+]]
+; CHECK:      irg  x1, x1
----------------
This might not be guaranteed to be x1


================
Comment at: llvm/test/CodeGen/AArch64/irg_sp_tagp.ll:76
+; CHECK-DAG:  sub  x0, x29, #[[OFS]]
 ; CHECK:      bl   use2
   %base = call i8* @llvm.aarch64.irg.sp(i64 0)
----------------
Check that addg is not there?


================
Comment at: llvm/test/CodeGen/AArch64/irg_sp_tagp.ll:94
 ; CHECK:      mov  x19, sp
-; CHECK:      irg  [[R:x[0-9]+]], x19
-; CHECK:      addg x1, [[R]], #[[OFS:[0-9]+]], #1
-; CHECK:      add  x0, x19, #[[OFS]]
+; CHECK:      add  x1, x19, #[[OFS:[0-9]+]]
+; CHECK:      irg  x1, x1
----------------
Might not be x1 here.


================
Comment at: llvm/test/CodeGen/AArch64/irg_sp_tagp.ll:95
+; CHECK:      add  x1, x19, #[[OFS:[0-9]+]]
+; CHECK:      irg  x1, x1
+; CHECK-DAG:  add  x0, x19, #[[OFS]]
----------------
Check that there is no addg.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D72365/new/

https://reviews.llvm.org/D72365