[PATCH] D75344: [PowerPC] Exploit VSX neg, abs and nabs instruction for f32

Qing Shan Zhang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Apr 23 22:46:47 PDT 2020


steven.zhang accepted this revision.
steven.zhang added a comment.
This revision is now accepted and ready to land.

The patch LGTM now with some comments update. But please hold for several days to see if Nemanjai(@nemanjai) has comments.



================
Comment at: llvm/lib/Target/PowerPC/PPCInstrVSX.td:1590
+  // Additional pattern for VSX f32 fneg
+  // XSNMSUBASP was firstly introduced in POWER ISA v2.07, while XSNEGDP exists
+  // in v2.06. Put this here to keep fnmsub in P7 targets.
----------------
The comments here is confusing. We are adding pattern for fneg and it has nothing to do with XSNMSUBASP though it is combined from fneg + fmsub. We need some comments indicate that, though xsnegdp is added in P7, we still only want to select it starting from P8, as we won't break the combine pattern for fneg + fmsub because XSNMSUBASP is only available starting from P8.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D75344/new/

https://reviews.llvm.org/D75344





More information about the llvm-commits mailing list