[PATCH] D78764: [RISCV] Update debug scratch register names

[Pengxuan Zheng via Phabricator via llvm-commits]

pzheng created this revision.
pzheng added reviewers: apazos, asb, lenary, luismarques.
Herald added subscribers: llvm-commits, evandro, sameer.abuasal, s.egerton, Jim, benna, psnobl, jocewei, PkmX, rkruppe, the_o, brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, MaskRay, jrtc27, shiva0217, kito-cheng, niosHD, sabuasal, simoncook, johnrusso, rbar, hiraditya.
Herald added a project: LLVM.

The RISC-V debug register was named dscratch in a previous draft of the RISC-V
debug mode spec. The number of registers has been increased to 2 in the latest
ratified version of the debug mode spec and the registers were named dscratch0
and dscratch1. We still support using the old register name "dscratch", but it
would be disassembled as "dscratch0" with this change.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78764

Files:
  llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp
  llvm/lib/Target/RISCV/RISCVSystemOperands.td
  llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h
  llvm/test/MC/RISCV/machine-csr-names.s

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