[PATCH] D78758: [x86] use vector instructions to lower even more FP->int->FP casts

[Sanjay Patel via Phabricator via llvm-commits]

spatel created this revision.
spatel added reviewers: RKSimon, craig.topper, pcordes.
Herald added subscribers: hiraditya, mcrosier.

This is another enhancement to D77895 <https://reviews.llvm.org/D77895>/D78362 <https://reviews.llvm.org/D78362> to avoid a round-trip from XMM->GPR->XMM. 
This time we handle the case of starting/ending with different FP types but always with signed i32 as the intermediate value.
I think this covers all of the faux vector optimization possibilities for pre-AVX512.

There is at least 1 other transform mentioned in PR36617:
https://bugs.llvm.org/show_bug.cgi?id=36617#c19
...where we fold an 'fpext' into a preceding 'sitofp'. I think we will want to handle that earlier (DAGCombiner or instcombine) because that's a target-independent optimization.


https://reviews.llvm.org/D78758

Files:
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/test/CodeGen/X86/ftrunc.ll

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