[PATCH] D78723: [AArch64][SVE] Custom lowering of floating-point reductions
Cullen Rhodes via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 23 09:11:25 PDT 2020
c-rhodes created this revision.
c-rhodes added reviewers: sdesmalen, efriedma, rengolin.
Herald added subscribers: danielkiss, psnobl, rkruppe, hiraditya, kristof.beyls, tschuett.
Herald added a project: LLVM.
This patch implements custom floating-point reduction ISD nodes that
have vector results, which are used to lower the following intrinsics:
- llvm.aarch64.sve.fadda
- llvm.aarch64.sve.faddv
- llvm.aarch64.sve.fmaxv
- llvm.aarch64.sve.fmaxnmv
- llvm.aarch64.sve.fminv
- llvm.aarch64.sve.fminnmv
SVE reduction instructions keep their result within a vector register,
with all other bits set to zero.
Changes in this patch were implemented by Paul Walker and Sander de
Smalen.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D78723
Files:
llvm/include/llvm/IR/IntrinsicsAArch64.td
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.h
llvm/lib/Target/AArch64/AArch64InstrFormats.td
llvm/lib/Target/AArch64/AArch64InstrInfo.td
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
llvm/lib/Target/AArch64/SVEInstrFormats.td
llvm/test/CodeGen/AArch64/sve-intrinsics-fp-reduce.ll
llvm/utils/TableGen/CodeGenDAGPatterns.cpp
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D78723.259592.patch
Type: text/x-patch
Size: 27181 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20200423/54a2a8b5/attachment-0001.bin>
More information about the llvm-commits
mailing list