[PATCH] D78265: [AArch64ConditionOptimizer] Fix missed optimization due to debug insts [10/10]

[Vedant Kumar via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGbf4c70b35562: [AArch64ConditionOptimizer] Fix missed optimization due to debug insts [11/14] (authored by vsk).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78265/new/

https://reviews.llvm.org/D78265

Files:
  llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
  llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll


Index: llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
===================================================================
--- llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
+++ llvm/test/CodeGen/AArch64/combine-comparisons-by-cse.ll
@@ -1,4 +1,4 @@
-; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s
+; RUN: llc -debugify-and-strip-all-safe < %s -mtriple=aarch64-linux-gnu | FileCheck %s
 
 ; marked as external to prevent possible optimizations
 @a = external global i32
Index: llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
===================================================================
--- llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
+++ llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp
@@ -158,32 +158,33 @@
       return nullptr;
 
   // Now find the instruction controlling the terminator.
-  for (MachineBasicBlock::iterator B = MBB->begin(); I != B;) {
-    --I;
-    assert(!I->isTerminator() && "Spurious terminator");
+  auto B = MBB->begin();
+  for (MachineInstr &I :
+       reversedInstructionsWithoutDebug(I == B ? I : std::prev(I), B)) {
+    assert(!I.isTerminator() && "Spurious terminator");
     // Check if there is any use of NZCV between CMP and Bcc.
-    if (I->readsRegister(AArch64::NZCV))
+    if (I.readsRegister(AArch64::NZCV))
       return nullptr;
-    switch (I->getOpcode()) {
+    switch (I.getOpcode()) {
     // cmp is an alias for subs with a dead destination register.
     case AArch64::SUBSWri:
     case AArch64::SUBSXri:
     // cmn is an alias for adds with a dead destination register.
     case AArch64::ADDSWri:
     case AArch64::ADDSXri: {
-      unsigned ShiftAmt = AArch64_AM::getShiftValue(I->getOperand(3).getImm());
-      if (!I->getOperand(2).isImm()) {
-        LLVM_DEBUG(dbgs() << "Immediate of cmp is symbolic, " << *I << '\n');
+      unsigned ShiftAmt = AArch64_AM::getShiftValue(I.getOperand(3).getImm());
+      if (!I.getOperand(2).isImm()) {
+        LLVM_DEBUG(dbgs() << "Immediate of cmp is symbolic, " << I << '\n');
         return nullptr;
-      } else if (I->getOperand(2).getImm() << ShiftAmt >= 0xfff) {
-        LLVM_DEBUG(dbgs() << "Immediate of cmp may be out of range, " << *I
+      } else if (I.getOperand(2).getImm() << ShiftAmt >= 0xfff) {
+        LLVM_DEBUG(dbgs() << "Immediate of cmp may be out of range, " << I
                           << '\n');
         return nullptr;
-      } else if (!MRI->use_empty(I->getOperand(0).getReg())) {
-        LLVM_DEBUG(dbgs() << "Destination of cmp is not dead, " << *I << '\n');
+      } else if (!MRI->use_nodbg_empty(I.getOperand(0).getReg())) {
+        LLVM_DEBUG(dbgs() << "Destination of cmp is not dead, " << I << '\n');
         return nullptr;
       }
-      return &*I;
+      return &I;
     }
     // Prevent false positive case like:
     // cmp      w19, #0


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