[PATCH] D70379: [AMDGPU] Reserving VGPR for future SGPR Spill

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp:271-278
+    MCPhysReg LowestFreeVGPRReg = AMDGPU::NoRegister;
+    for (MCPhysReg Reg : AMDGPU::VGPR_32RegClass.getRegisters()) {
+      if (!MRI.isPhysRegUsed(Reg)) {
+        LowestFreeVGPRReg = Reg;
+        break;
+      }
+    }
----------------
Should split into another function. It also isn't ensuring it's a CSR? 


================
Comment at: llvm/lib/Target/AMDGPU/SILowerSGPRSpills.cpp:318
         MBB.addLiveIn(SSpill.VGPR);
+      // MBB.addLiveIn(LowestFreeVGPRReg);
 
----------------
Commented out code


================
Comment at: llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.h:488-489
 
+  Register VGPRReservedForSGPRSpill;
+  Optional<int> ReservedVGPRforSGPRIndex;
+
----------------
This shouldn't be separate from the existing SGPR spill infrastructure. This is only pre-allocating one register


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D70379/new/

https://reviews.llvm.org/D70379