[PATCH] D78312: [AMDGPU] Add 192-bit register classes

[Jay Foad via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGdbdffe3ee9d6: [AMDGPU] Add 192-bit register classes (authored by foad).

Changed prior to commit:
  https://reviews.llvm.org/D78312?vs=258950&id=259250#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78312/new/

https://reviews.llvm.org/D78312

Files:
  llvm/lib/Target/AMDGPU/AMDGPUAsmPrinter.cpp
  llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  llvm/lib/Target/AMDGPU/MCTargetDesc/SIMCCodeEmitter.cpp
  llvm/lib/Target/AMDGPU/SIISelLowering.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
  llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte-xfail.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
  llvm/test/CodeGen/AMDGPU/GlobalISel/zextload-xfail.ll
  llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
  llvm/test/CodeGen/AMDGPU/ipra-regmask.ll

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