[PATCH] D77469: [llvm] NFC: Fix trivial typo in rst and td files

[Kazuaki Ishizaki via Phabricator via llvm-commits]

kiszk updated this revision to Diff 259065.
kiszk added a comment.

Rebase and resolve conflicts in llvm/lib/Target/PowerPC/PPCScheduleP9.td and llvm/docs/AMDGPUUsage.rst


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D77469/new/

https://reviews.llvm.org/D77469

Files:
  llvm/docs/Extensions.rst
  llvm/docs/HowToUseInstrMappings.rst
  llvm/docs/LangRef.rst
  llvm/docs/ProgrammersManual.rst
  llvm/docs/Proposals/GitHubMove.rst
  llvm/docs/TableGen/LangRef.rst
  llvm/docs/tutorial/BuildingAJIT2.rst
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/include/llvm/IR/IntrinsicsARM.td
  llvm/include/llvm/IR/IntrinsicsPowerPC.td
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/include/llvm/Target/Target.td
  llvm/include/llvm/Target/TargetItinerary.td
  llvm/include/llvm/Target/TargetSchedule.td
  llvm/include/llvm/Target/TargetSelectionDAG.td
  llvm/lib/Target/AArch64/AArch64.td
  llvm/lib/Target/AArch64/AArch64InstrFormats.td
  llvm/lib/Target/AArch64/AArch64RegisterInfo.td
  llvm/lib/Target/AArch64/AArch64SystemOperands.td
  llvm/lib/Target/AMDGPU/AMDGPUGISel.td
  llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td
  llvm/lib/Target/AMDGPU/BUFInstructions.td
  llvm/lib/Target/AMDGPU/DSInstructions.td
  llvm/lib/Target/AMDGPU/FLATInstructions.td
  llvm/lib/Target/AMDGPU/MIMGInstructions.td
  llvm/lib/Target/AMDGPU/SIInstrInfo.td
  llvm/lib/Target/AMDGPU/SIInstructions.td
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/lib/Target/AMDGPU/SISchedule.td
  llvm/lib/Target/AMDGPU/SMInstructions.td
  llvm/lib/Target/AMDGPU/SOPInstructions.td
  llvm/lib/Target/AMDGPU/VIInstructions.td
  llvm/lib/Target/AMDGPU/VOP1Instructions.td
  llvm/lib/Target/AMDGPU/VOP2Instructions.td
  llvm/lib/Target/AMDGPU/VOP3Instructions.td
  llvm/lib/Target/AMDGPU/VOP3PInstructions.td
  llvm/lib/Target/AMDGPU/VOPCInstructions.td
  llvm/lib/Target/AMDGPU/VOPInstructions.td
  llvm/lib/Target/ARC/ARCInstrInfo.td
  llvm/lib/Target/ARM/ARMInstrCDE.td
  llvm/lib/Target/ARM/ARMInstrInfo.td
  llvm/lib/Target/ARM/ARMInstrMVE.td
  llvm/lib/Target/ARM/ARMInstrNEON.td
  llvm/lib/Target/ARM/ARMInstrThumb.td
  llvm/lib/Target/ARM/ARMInstrThumb2.td
  llvm/lib/Target/ARM/ARMScheduleA57.td
  llvm/lib/Target/ARM/ARMScheduleSwift.td
  llvm/lib/Target/Hexagon/HexagonIICScalar.td
  llvm/lib/Target/Hexagon/HexagonInstrFormats.td
  llvm/lib/Target/Hexagon/HexagonInstrFormatsV65.td
  llvm/lib/Target/Hexagon/HexagonPseudo.td
  llvm/lib/Target/Mips/MicroMipsInstrFormats.td
  llvm/lib/Target/Mips/MicroMipsInstrInfo.td
  llvm/lib/Target/Mips/Mips16InstrInfo.td
  llvm/lib/Target/Mips/MipsInstrInfo.td
  llvm/lib/Target/PowerPC/PPC.td
  llvm/lib/Target/PowerPC/PPCInstrInfo.td
  llvm/lib/Target/PowerPC/PPCInstrVSX.td
  llvm/lib/Target/PowerPC/PPCRegisterInfo.td
  llvm/lib/Target/PowerPC/PPCScheduleP9.td
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/lib/Target/Sparc/SparcCallingConv.td
  llvm/lib/Target/Sparc/SparcInstrInfo.td
  llvm/lib/Target/Sparc/SparcSchedule.td
  llvm/lib/Target/SystemZ/SystemZInstrFormats.td
  llvm/lib/Target/SystemZ/SystemZInstrVector.td
  llvm/lib/Target/SystemZ/SystemZPatterns.td
  llvm/lib/Target/SystemZ/SystemZProcessors.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrCall.td
  llvm/lib/Target/WebAssembly/WebAssemblyInstrRef.td
  llvm/lib/Target/X86/X86.td
  llvm/lib/Target/X86/X86InstrAVX512.td
  llvm/lib/Target/X86/X86InstrCompiler.td
  llvm/lib/Target/X86/X86InstrFMA.td
  llvm/lib/Target/X86/X86InstrFPStack.td
  llvm/lib/Target/X86/X86InstrInfo.cpp
  llvm/lib/Target/X86/X86InstrSSE.td
  llvm/lib/Target/X86/X86RegisterInfo.td
  llvm/lib/Target/X86/X86SchedBroadwell.td
  llvm/lib/Target/X86/X86SchedHaswell.td
  llvm/lib/Target/X86/X86SchedSandyBridge.td
  llvm/lib/Target/X86/X86SchedSkylakeClient.td
  llvm/lib/Target/X86/X86SchedSkylakeServer.td
  llvm/test/TableGen/ConcatenatedSubregs.td
  llvm/test/TableGen/prep-region-processing.td

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