[PATCH] D78586: [MachineVerifier] Add more checks for registers in live-in lists.
Eli Friedman via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 21 13:33:36 PDT 2020
efriedma created this revision.
efriedma added reviewers: kparzysz, arsenm, craig.topper, RKSimon, dmgreen.
Herald added subscribers: luismarques, steven.zhang, s.egerton, lenary, wuzish, PkmX, jfb, simoncook, hiraditya, kristof.beyls, arichardson, tpr, wdng, sdardis.
Herald added a project: LLVM.
Excluding landing pads, a register that's live-in should be live-out of each of its predecessors. Expand the check for this to include allocatable registers, and registers with aliases.
We do a relatively relaxed check for registers with aliases: some register that aliases the register in question must be live-out of each predecessor. In some cases, it might make sense to try to do something more strict, but this is enough to catch a lot of interesting cases.
Currently guarded by a flag because a bunch of targets have at least one regression test failure with this and expensive checks enabled. In particular, there are failures for AArch64, AMDGPU, ARM, Hexagon, Mips, PowerPC, RISC-V, SystemZ, and X86. I'd appreciate if people working with those targets would look into this.
SystemZ only fails on one MIR test, and I think that's a bug in the test, not the backend. The other backends appear to have at least one real bug.
There's a cluster of failures involving code failing to compute live-ins correctly when expanding atomic pseudo-instructions. This affects the ARM, Mips, and RISC-V backend. Might make sense to address them together, even though the code is separate.
For x86, one of the failing tests involves callbr; maybe related to D75098 <https://reviews.llvm.org/D75098>?
Complete list of failures, for reference:
LLVM :: CodeGen/AArch64/machine-outliner-retaddr-sign-regsave.mir
LLVM :: CodeGen/AMDGPU/constant-fold-imm-immreg.mir
LLVM :: CodeGen/AMDGPU/cross-block-use-is-not-abi-copy.ll
LLVM :: CodeGen/AMDGPU/fold-immediate-operand-shrink.mir
LLVM :: CodeGen/AMDGPU/frame-lowering-fp-adjusted.mir
LLVM :: CodeGen/AMDGPU/global_smrd_cfg.ll
LLVM :: CodeGen/ARM/cmpxchg-O0.ll
LLVM :: CodeGen/Hexagon/Atomics.ll
LLVM :: CodeGen/Hexagon/aggr-licm.ll
LLVM :: CodeGen/Hexagon/bit-extract-off.ll
LLVM :: CodeGen/Hexagon/concat-vectors-legalize.ll
LLVM :: CodeGen/Hexagon/deflate.ll
LLVM :: CodeGen/Hexagon/frame-offset-overflow.ll
LLVM :: CodeGen/Hexagon/i128-bitop.ll
LLVM :: CodeGen/Hexagon/livephysregs-lane-masks.mir
LLVM :: CodeGen/Hexagon/livephysregs-lane-masks2.mir
LLVM :: CodeGen/Hexagon/packetize-impdef-1.ll
LLVM :: CodeGen/Hexagon/reg-scav-imp-use-dbl-vec.ll
LLVM :: CodeGen/Hexagon/reg-scavengebug-2.ll
LLVM :: CodeGen/Hexagon/reg-scavengebug-4.ll
LLVM :: CodeGen/Hexagon/swp-conv3x3-nested.ll
LLVM :: CodeGen/Hexagon/swp-epilog-phi6.ll
LLVM :: CodeGen/Hexagon/swp-epilog-phi7.ll
LLVM :: CodeGen/Hexagon/swp-order-carried.ll
LLVM :: CodeGen/Hexagon/swp-order-deps6.ll
LLVM :: CodeGen/Hexagon/swp-reuse-phi-4.ll
LLVM :: CodeGen/Hexagon/swp-reuse-phi-6.ll
LLVM :: CodeGen/Hexagon/swp-sigma.ll
LLVM :: CodeGen/Hexagon/v6-spill1.ll
LLVM :: CodeGen/Hexagon/v60-vecpred-spill.ll
LLVM :: CodeGen/Hexagon/v60Vasr.ll
LLVM :: CodeGen/Hexagon/vect-regpairs.ll
LLVM :: CodeGen/Hexagon/vect/vect-cst-v4i8.ll
LLVM :: CodeGen/Hexagon/vect/vect-cst.ll
LLVM :: CodeGen/Hexagon/vect/vect-vsplatb.ll
LLVM :: CodeGen/Hexagon/vect/vect-xor.ll
LLVM :: CodeGen/Hexagon/vgather-packetize.mir
LLVM :: CodeGen/Hexagon/vmpa-halide-test.ll
LLVM :: CodeGen/Mips/atomic-min-max.ll
LLVM :: CodeGen/Mips/atomic.ll
LLVM :: CodeGen/Mips/atomic64.ll
LLVM :: CodeGen/Mips/atomicCmpSwapPW.ll
LLVM :: CodeGen/Mips/micromips-atomic1.ll
LLVM :: CodeGen/PowerPC/2006-11-10-DAGCombineMiscompile.ll
LLVM :: CodeGen/PowerPC/2008-03-17-RegScavengerCrash.ll
LLVM :: CodeGen/PowerPC/2008-06-23-LiveVariablesCrash.ll
LLVM :: CodeGen/PowerPC/2008-10-28-f128-i32.ll
LLVM :: CodeGen/PowerPC/2011-12-06-SpillAndRestoreCR.ll
LLVM :: CodeGen/PowerPC/2012-09-16-TOC-entry-check.ll
LLVM :: CodeGen/PowerPC/absol-jump-table-enabled.ll
LLVM :: CodeGen/PowerPC/crbit-asm.ll
LLVM :: CodeGen/PowerPC/crbits.ll
LLVM :: CodeGen/PowerPC/ctrloop-sh.ll
LLVM :: CodeGen/PowerPC/ctrloops.ll
LLVM :: CodeGen/PowerPC/expand-contiguous-isel.ll
LLVM :: CodeGen/PowerPC/expand-foldable-isel.ll
LLVM :: CodeGen/PowerPC/expand-isel-1.mir
LLVM :: CodeGen/PowerPC/expand-isel-2.mir
LLVM :: CodeGen/PowerPC/expand-isel-3.mir
LLVM :: CodeGen/PowerPC/expand-isel-4.mir
LLVM :: CodeGen/PowerPC/expand-isel-5.mir
LLVM :: CodeGen/PowerPC/expand-isel-6.mir
LLVM :: CodeGen/PowerPC/expand-isel-7.mir
LLVM :: CodeGen/PowerPC/expand-isel-8.mir
LLVM :: CodeGen/PowerPC/expand-isel-liveness.mir
LLVM :: CodeGen/PowerPC/expand-isel.ll
LLVM :: CodeGen/PowerPC/fast-isel-conversion.ll
LLVM :: CodeGen/PowerPC/float-to-int.ll
LLVM :: CodeGen/PowerPC/fold-zero.ll
LLVM :: CodeGen/PowerPC/fp-to-int-to-fp.ll
LLVM :: CodeGen/PowerPC/fp128-libcalls.ll
LLVM :: CodeGen/PowerPC/i1-ext-fold.ll
LLVM :: CodeGen/PowerPC/i1-to-double.ll
LLVM :: CodeGen/PowerPC/i64_fp_round.ll
LLVM :: CodeGen/PowerPC/ifcvt.ll
LLVM :: CodeGen/PowerPC/int-fp-conv-1.ll
LLVM :: CodeGen/PowerPC/isel.ll
LLVM :: CodeGen/PowerPC/mul-with-overflow.ll
LLVM :: CodeGen/PowerPC/optcmp.ll
LLVM :: CodeGen/PowerPC/p8-isel-sched.ll
LLVM :: CodeGen/PowerPC/ppc-crbits-onoff.ll
LLVM :: CodeGen/PowerPC/ppc-vaarg-agg.ll
LLVM :: CodeGen/PowerPC/ppc32-i64-to-float-conv.ll
LLVM :: CodeGen/PowerPC/ppc64-toc.ll
LLVM :: CodeGen/PowerPC/ppcf128sf.ll
LLVM :: CodeGen/PowerPC/pr43976.ll
LLVM :: CodeGen/PowerPC/prolog_vec_spills.mir
LLVM :: CodeGen/PowerPC/save-cr-ppc32svr4.ll
LLVM :: CodeGen/PowerPC/save-crbp-ppc32svr4.ll
LLVM :: CodeGen/PowerPC/select-i1-vs-i1.ll
LLVM :: CodeGen/PowerPC/select_const.ll
LLVM :: CodeGen/PowerPC/setcr_bc2.mir
LLVM :: CodeGen/PowerPC/setcr_bc3.mir
LLVM :: CodeGen/PowerPC/smulfixsat.ll
LLVM :: CodeGen/PowerPC/spe.ll
LLVM :: CodeGen/PowerPC/subreg-postra.ll
LLVM :: CodeGen/PowerPC/umulfixsat.ll
LLVM :: CodeGen/PowerPC/umulo-128-legalisation-lowering.ll
LLVM :: CodeGen/PowerPC/varargs.ll
LLVM :: CodeGen/RISCV/atomic-cmpxchg-flag.ll
LLVM :: CodeGen/RISCV/atomic-cmpxchg.ll
LLVM :: CodeGen/RISCV/atomic-rmw.ll
LLVM :: CodeGen/RISCV/shrinkwrap.ll
LLVM :: CodeGen/SystemZ/load-and-test.mir
LLVM :: CodeGen/Thumb/thumb-shrink-wrapping.ll
LLVM :: CodeGen/X86/2009-07-15-CoalescerBug.ll
LLVM :: CodeGen/X86/block-placement.mir
LLVM :: CodeGen/X86/callbr-asm-outputs.ll
LLVM :: CodeGen/X86/dbg-changes-codegen-branch-folding2.mir
LLVM :: CodeGen/X86/icall-branch-funnel.ll
LLVM :: CodeGen/X86/implicit-null-checks.mir
LLVM :: CodeGen/X86/implicit-null-chk-reg-rewrite.mir
LLVM :: CodeGen/X86/leaFixup32.mir
LLVM :: CodeGen/X86/leaFixup64.mir
LLVM :: CodeGen/X86/pr38952.mir
LLVM :: CodeGen/X86/win_coreclr_chkstk_liveins.mir
LLVM :: DebugInfo/MIR/ARM/subregister-full-piece.mir
LLVM :: DebugInfo/MIR/X86/live-debug-values-reg-copy.mir
LLVM :: DebugInfo/X86/live-debug-values-constprop.mir
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D78586
Files:
llvm/lib/CodeGen/MachineVerifier.cpp
Index: llvm/lib/CodeGen/MachineVerifier.cpp
===================================================================
--- llvm/lib/CodeGen/MachineVerifier.cpp
+++ llvm/lib/CodeGen/MachineVerifier.cpp
@@ -81,6 +81,11 @@
using namespace llvm;
+static cl::opt<bool> VerifierStrictLivein(
+ "machine-verifier-strict-livein", cl::Hidden,
+ cl::desc("Enable strict verification of basic block live-ins"),
+ cl::init(false));
+
namespace {
struct MachineVerifier {
@@ -2434,19 +2439,36 @@
// that the register is in regsLiveOut of each predecessor block. Since
// this must come from a definition in the predecesssor or its live-in
// list, this will catch a live-through case where the predecessor does not
- // have the register in its live-in list. This currently only checks
- // registers that have no aliases, are not allocatable and are not
- // reserved, which could mean a condition code register for instance.
- if (MRI->tracksLiveness())
- for (const auto &MBB : *MF)
+ // have the register in its live-in list.
+ if (MRI->tracksLiveness()) {
+ for (const auto &MBB : *MF) {
+ if (MBB.isEHPad())
+ continue;
for (MachineBasicBlock::RegisterMaskPair P : MBB.liveins()) {
MCPhysReg LiveInReg = P.PhysReg;
+
+ // We don't track liveness for reserved registers.
+ if (isReserved(LiveInReg))
+ continue;
+
+ // Strict checking of allocatable/aliased registers is controlled by
+ // a flag to deal with regression test failures.
bool hasAliases = MCRegAliasIterator(LiveInReg, TRI, false).isValid();
- if (hasAliases || isAllocatable(LiveInReg) || isReserved(LiveInReg))
+ if (!VerifierStrictLivein && (hasAliases || isAllocatable(LiveInReg)))
continue;
+
for (const MachineBasicBlock *Pred : MBB.predecessors()) {
BBInfo &PInfo = MBBInfoMap[Pred];
- if (!PInfo.regsLiveOut.count(LiveInReg)) {
+ MCRegAliasIterator AliasingRegs(LiveInReg, TRI, true);
+ bool FoundPred = false;
+ while (AliasingRegs.isValid()) {
+ if (PInfo.regsLiveOut.count(*AliasingRegs)) {
+ FoundPred = true;
+ break;
+ }
+ ++AliasingRegs;
+ }
+ if (!FoundPred) {
report("Live in register not found to be live out from predecessor.",
&MBB);
errs() << TRI->getName(LiveInReg)
@@ -2455,6 +2477,8 @@
}
}
}
+ }
+ }
for (auto CSInfo : MF->getCallSitesInfo())
if (!CSInfo.first->isCall())
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