[llvm] 8387bee - [llvm] [X86] Fixed type bug in vselect for AVX masked load

[via llvm-commits]

Author: aartbik
Date: 2020-04-21T11:11:35-07:00
New Revision: 8387bee94d6e7e7ad6f07be18bb09488978e7fb0

URL: https://github.com/llvm/llvm-project/commit/8387bee94d6e7e7ad6f07be18bb09488978e7fb0
DIFF: https://github.com/llvm/llvm-project/commit/8387bee94d6e7e7ad6f07be18bb09488978e7fb0.diff

LOG: [llvm] [X86] Fixed type bug in vselect for AVX masked load

Summary:
Bugzilla issue 45563
https://bugs.llvm.org/show_bug.cgi?id=45563

Reviewers: nicolasvasilache, mehdi_amini, craig.topper

Reviewed By: craig.topper

Subscribers: RKSimon, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78527

Added: 
    llvm/test/CodeGen/X86/pr45563.ll

Modified: 
    llvm/lib/Target/X86/X86ISelLowering.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index 8457bce9a04b..13c54c5f13db 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -28772,8 +28772,7 @@ static SDValue LowerMLOAD(SDValue Op, const X86Subtarget &Subtarget,
         N->getMemOperand(), N->getAddressingMode(), N->getExtensionType(),
         N->isExpandingLoad());
     // Emit a blend.
-    SDValue Select = DAG.getNode(ISD::VSELECT, dl, MaskVT, Mask, NewLoad,
-                                 PassThru);
+    SDValue Select = DAG.getNode(ISD::VSELECT, dl, VT, Mask, NewLoad, PassThru);
     return DAG.getMergeValues({ Select, NewLoad.getValue(1) }, dl);
   }
 
@@ -28809,10 +28808,10 @@ static SDValue LowerMLOAD(SDValue Op, const X86Subtarget &Subtarget,
       PassThru, N->getMemoryVT(), N->getMemOperand(), N->getAddressingMode(),
       N->getExtensionType(), N->isExpandingLoad());
 
-  SDValue Exract = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT,
-                               NewLoad.getValue(0),
-                               DAG.getIntPtrConstant(0, dl));
-  SDValue RetOps[] = {Exract, NewLoad.getValue(1)};
+  SDValue Extract =
+      DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, VT, NewLoad.getValue(0),
+                  DAG.getIntPtrConstant(0, dl));
+  SDValue RetOps[] = {Extract, NewLoad.getValue(1)};
   return DAG.getMergeValues(RetOps, dl);
 }
 

diff  --git a/llvm/test/CodeGen/X86/pr45563.ll b/llvm/test/CodeGen/X86/pr45563.ll
new file mode 100644
index 000000000000..3fbd991729d5
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr45563.ll
@@ -0,0 +1,21 @@
+; RUN: llc < %s -debug-only=isel -O3 -mattr=avx  2>&1 | FileCheck %s
+
+; Bug 45563:
+; The LowerMLOAD() method AVX masked load branch should
+; use the operand vector type rather than the mask type.
+; Given, for example:
+;   v4f64,ch = masked_load ..
+; The select should be:
+;   v4f64 = vselect ..
+; instead of:
+;   v4i64 = vselect ..
+
+define <16 x double> @bug45563(<16 x double>* %addr, <16 x double> %dst, <16 x i64> %e, <16 x i64> %f) {
+; CHECK-LABEL: bug45563:
+; CHECK:       v4f64 = vselect
+  %mask = icmp slt <16 x i64> %e, %f
+  %res = call <16 x double> @llvm.masked.load.v16f64.p0v16f64(<16 x double>* %addr, i32 4, <16 x i1>%mask, <16 x double> %dst)
+  ret <16 x double> %res
+}
+
+declare <16 x double> @llvm.masked.load.v16f64.p0v16f64(<16 x double>* %addr, i32 %align, <16 x i1> %mask, <16 x double> %dst)