[llvm] e477915 - [PowerPC] Add a new test case expand-isel-liveness.mir
Kang Zhang via llvm-commits
llvm-commits at lists.llvm.org
Tue Apr 21 09:20:23 PDT 2020
Author: Kang Zhang
Date: 2020-04-21T16:00:34Z
New Revision: e477915bfe5ed11e7010ccf8483eaeea6e5d8809
URL: https://github.com/llvm/llvm-project/commit/e477915bfe5ed11e7010ccf8483eaeea6e5d8809
DIFF: https://github.com/llvm/llvm-project/commit/e477915bfe5ed11e7010ccf8483eaeea6e5d8809.diff
LOG: [PowerPC] Add a new test case expand-isel-liveness.mir
Added:
llvm/test/CodeGen/PowerPC/expand-isel-liveness.mir
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/PowerPC/expand-isel-liveness.mir b/llvm/test/CodeGen/PowerPC/expand-isel-liveness.mir
new file mode 100644
index 000000000000..9decf6a79ece
--- /dev/null
+++ b/llvm/test/CodeGen/PowerPC/expand-isel-liveness.mir
@@ -0,0 +1,50 @@
+# RUN: llc -mtriple powerpc64-unknown-linux-gnu -run-pass=ppc-expand-isel -o \
+# RUN: - %s -verify-machineinstrs | FileCheck %s
+
+---
+name: expand_isel_liveness
+tracksRegLiveness: true
+registers: []
+liveins:
+ - { reg: '$x3', virtual-reg: '' }
+ - { reg: '$x4', virtual-reg: '' }
+ - { reg: '$x5', virtual-reg: '' }
+ - { reg: '$x6', virtual-reg: '' }
+body: |
+ bb.0:
+ liveins: $x3, $x4, $x5, $x6
+
+ renamable $x8 = MULLD renamable $x5, renamable $x4
+ renamable $cr5 = CMPDI renamable $x3, 0
+ dead renamable $x9 = MULHDU_rec renamable $x3, renamable $x6, implicit-def $cr0
+ renamable $x3 = MULLD killed renamable $x3, renamable $x6
+ $cr1 = MCRF killed $cr0
+ renamable $x3 = ADD8 killed renamable $x3, killed renamable $x8
+ renamable $cr0 = CMPDI renamable $x5, 0
+ renamable $cr5lt = CRNOR killed renamable $cr0eq, killed renamable $cr5eq, implicit $cr5, implicit $cr0
+ renamable $cr0 = CMPLDI renamable $x3, 0
+ renamable $x8 = MULHDU renamable $x4, renamable $x6
+ renamable $x3 = ADD8 renamable $x8, killed renamable $x3
+ renamable $cr6 = CMPLD renamable $x3, killed renamable $x8
+ renamable $cr5gt = CRANDC killed renamable $cr6lt, killed renamable $cr0eq, implicit $cr0, implicit $cr6
+ renamable $cr5lt = CRORC killed renamable $cr5lt, killed renamable $cr1eq, implicit $cr1
+ renamable $x7 = LI8 1
+ dead renamable $x5 = MULHDU_rec killed renamable $x5, renamable $x4, implicit-def $cr0
+ renamable $cr5lt = CRORC killed renamable $cr5lt, killed renamable $cr0eq, implicit $cr0
+ renamable $cr5lt = CRNOR killed renamable $cr5lt, killed renamable $cr5gt
+ renamable $x4 = MULLD killed renamable $x4, killed renamable $x6
+ renamable $x5 = ISEL8 $zero8, killed renamable $x7, killed renamable $cr5lt
+ BLR8 implicit $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5
+
+ ; CHECK-LABEL: expand_isel_liveness
+ ; CHECK: bb.1:
+ ; CHECK: liveins: $x7
+ ; CHECK: renamable $x5 = ORI8 killed renamable $x7, 0
+ ; CHECK: B %bb.3
+ ; CHECK: bb.2:
+ ; CHECK: liveins: $zero8
+ ; CHECK: renamable $x5 = ADDI8 $zero8, 0
+ ; CHECK: bb.3:
+ ; CHECK: liveins: $x3, $x4, $x5, $x6, $cr1lt, $cr1gt, $x3, $cr6lt, $cr0eq, $r3, $cr5un, $cr1eq, $cr1un, $cr6un, $cr0lt, $cr0gt, $cr6gt, $cr0un, $cr1, $cr6, $cr5eq, $x8, $r8, $cr6eq, $x4, $r4, $cr0, $cr5gt, $cr5, $cr5lt, $x7, $r7, $x5, $r5, $x5, $zero8, $x7, $cr5lt
+ ; CHECK: BLR8 implicit $lr8, implicit $rm, implicit killed $x3, implicit killed $x4, implicit killed $x5
+...
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