[PATCH] D77448: [PowerPC] Canonicalize shuffles to match more single-instruction masks on LE

[Amy Kwan via Phabricator via llvm-commits]

amyk added inline comments.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13850
+SDValue PPCTargetLowering::combineVectorShuffle(ShuffleVectorSDNode *SVN,
+                                                SelectionDAG &DAG) const {
+  SDValue LHS = SVN->getOperand(0);
----------------
I see that our other combine functions have an assert in the beginning checking the opcode. It might make sense to have one here checking `SVN->getOpcode() == ISD::VECTOR_SHUFFLE`?


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13868
+  }
+  bool IsLHSSplat = isSplatBV(LHS);
+  bool IsRHSSplat = isSplatBV(RHS);
----------------
Is it possible to add a comment regarding the splats here? Or is the comment above supposed to explain this bit, too?


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:13884
+  // and we have elements coming in from the splat at indices that are not
+  // condusive to using a merge.
+  // Example:
----------------
s/condusive/conducive


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  https://reviews.llvm.org/D77448/new/

https://reviews.llvm.org/D77448