[llvm] a0b1616 - [ARM] Regenerate tests. NFC
David Green via llvm-commits
llvm-commits at lists.llvm.org
Sun Apr 19 05:46:02 PDT 2020
Author: David Green
Date: 2020-04-19T13:45:39+01:00
New Revision: a0b161635960f943fe958500b29dcccb7ceec725
URL: https://github.com/llvm/llvm-project/commit/a0b161635960f943fe958500b29dcccb7ceec725
DIFF: https://github.com/llvm/llvm-project/commit/a0b161635960f943fe958500b29dcccb7ceec725.diff
LOG: [ARM] Regenerate tests. NFC
Added:
Modified:
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
llvm/test/CodeGen/Thumb2/mve-intrinsics/predicates.ll
llvm/test/CodeGen/Thumb2/mve-intrinsics/vadc-multiple.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
index 905b6d14bf08..b01c98cedeb7 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-float-loops.ll
@@ -1803,7 +1803,7 @@ define arm_aapcs_vfpcc float @half_short_mac(half* nocapture readonly %a, i16* n
; CHECK-NEXT: adds r2, r0, #4
; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB11_5: @ %for.body
-; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
; CHECK-NEXT: ldrsh.w r4, [r3, #2]
; CHECK-NEXT: vldr.16 s2, [r2, #2]
; CHECK-NEXT: add.w r12, r12, #4
diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
index 0b8a20e82569..b76ca06ecec3 100644
--- a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
+++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/mve-tail-data-types.ll
@@ -377,24 +377,24 @@ define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_char(i8* nocapture readonly
; CHECK-NEXT: cmp r6, r1
; CHECK-NEXT: add.w r5, r0, r12
; CHECK-NEXT: cset lr, hi
-; CHECK-NEXT: cmp r4, r3
+; CHECK-NEXT: cmp r4, r3
; CHECK-NEXT: cset r4, hi
-; CHECK-NEXT: cmp r6, r0
+; CHECK-NEXT: cmp r6, r0
; CHECK-NEXT: cset r6, hi
-; CHECK-NEXT: cmp r5, r3
+; CHECK-NEXT: cmp r5, r3
; CHECK-NEXT: cset r5, hi
; CHECK-NEXT: ands r5, r6
; CHECK-NEXT: movs r6, #1
; CHECK-NEXT: lsls r5, r5, #31
-; CHECK-NEXT: itt eq
+; CHECK-NEXT: itt eq
; CHECK-NEXT: andeq.w r5, r4, lr
; CHECK-NEXT: lslseq.w r5, r5, #31
-; CHECK-NEXT: beq .LBB5_4
+; CHECK-NEXT: beq .LBB5_4
; CHECK-NEXT: @ %bb.2: @ %for.body.preheader
-; CHECK-NEXT: sub.w r5, r12, #1
-; CHECK-NEXT: and r9, r12, #3
-; CHECK-NEXT: cmp r5, #3
-; CHECK-NEXT: bhs .LBB5_6
+; CHECK-NEXT: sub.w r5, r12, #1
+; CHECK-NEXT: and r9, r12, #3
+; CHECK-NEXT: cmp r5, #3
+; CHECK-NEXT: bhs .LBB5_6
; CHECK-NEXT: @ %bb.3:
; CHECK-NEXT: mov.w r12, #0
; CHECK-NEXT: b .LBB5_8
@@ -418,28 +418,28 @@ define arm_aapcs_vfpcc void @test_vec_mul_scalar_add_char(i8* nocapture readonly
; CHECK-NEXT: adds r6, r1, #1
; CHECK-NEXT: dls lr, lr
; CHECK-NEXT: .LBB5_7: @ %for.body
-; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
-; CHECK-NEXT: ldrb r8, [r5, #-3]
-; CHECK-NEXT: add.w r12, r12, #4
-; CHECK-NEXT: ldrb r7, [r6, #-1]
-; CHECK-NEXT: smlabb r7, r7, r8, r2
-; CHECK-NEXT: str r7, [r4, #-8]
-; CHECK-NEXT: ldrb r8, [r5, #-2]
-; CHECK-NEXT: ldrb r7, [r6]
-; CHECK-NEXT: smlabb r7, r7, r8, r2
-; CHECK-NEXT: str r7, [r4, #-4]
-; CHECK-NEXT: ldrb r8, [r5, #-1]
-; CHECK-NEXT: ldrb r7, [r6, #1]
-; CHECK-NEXT: smlabb r7, r7, r8, r2
-; CHECK-NEXT: str r7, [r4]
-; CHECK-NEXT: ldrb.w r8, [r5]
-; CHECK-NEXT: adds r5, #4
-; CHECK-NEXT: ldrb r7, [r6, #2]
-; CHECK-NEXT: adds r6, #4
-; CHECK-NEXT: smlabb r7, r7, r8, r2
-; CHECK-NEXT: str r7, [r4, #4]
-; CHECK-NEXT: adds r4, #16
-; CHECK-NEXT: le lr, .LBB5_7
+; CHECK-NEXT: @ =>This Inner Loop Header: Depth=1
+; CHECK-NEXT: ldrb r8, [r5, #-3]
+; CHECK-NEXT: add.w r12, r12, #4
+; CHECK-NEXT: ldrb r7, [r6, #-1]
+; CHECK-NEXT: smlabb r7, r7, r8, r2
+; CHECK-NEXT: str r7, [r4, #-8]
+; CHECK-NEXT: ldrb r8, [r5, #-2]
+; CHECK-NEXT: ldrb r7, [r6]
+; CHECK-NEXT: smlabb r7, r7, r8, r2
+; CHECK-NEXT: str r7, [r4, #-4]
+; CHECK-NEXT: ldrb r8, [r5, #-1]
+; CHECK-NEXT: ldrb r7, [r6, #1]
+; CHECK-NEXT: smlabb r7, r7, r8, r2
+; CHECK-NEXT: str r7, [r4]
+; CHECK-NEXT: ldrb.w r8, [r5]
+; CHECK-NEXT: adds r5, #4
+; CHECK-NEXT: ldrb r7, [r6, #2]
+; CHECK-NEXT: adds r6, #4
+; CHECK-NEXT: smlabb r7, r7, r8, r2
+; CHECK-NEXT: str r7, [r4, #4]
+; CHECK-NEXT: adds r4, #16
+; CHECK-NEXT: le lr, .LBB5_7
; CHECK-NEXT: .LBB5_8: @ %for.cond.cleanup.loopexit.unr-lcssa
; CHECK-NEXT: wls lr, r9, .LBB5_11
; CHECK-NEXT: @ %bb.9: @ %for.body.epil.preheader
diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/predicates.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/predicates.ll
index f5b541203f6a..23220bb552f8 100644
--- a/llvm/test/CodeGen/Thumb2/mve-intrinsics/predicates.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/predicates.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: opt -instcombine %s | llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - | FileCheck %s
declare <16 x i1> @llvm.arm.mve.vctp8(i32)
diff --git a/llvm/test/CodeGen/Thumb2/mve-intrinsics/vadc-multiple.ll b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vadc-multiple.ll
index c0a095327076..2bc8c5f589c3 100644
--- a/llvm/test/CodeGen/Thumb2/mve-intrinsics/vadc-multiple.ll
+++ b/llvm/test/CodeGen/Thumb2/mve-intrinsics/vadc-multiple.ll
@@ -1,3 +1,4 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: opt -instcombine -S %s | FileCheck --check-prefix=IR %s
; RUN: opt -instcombine %s | llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -O3 -o - | FileCheck --check-prefix=ASM %s
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