[llvm] a5d161c - [PowerPC] Don't use rldicl for PPC32

[Fangrui Song via llvm-commits]

Author: LemonBoy
Date: 2020-04-18T17:24:25-07:00
New Revision: a5d161c119d5a03c1ce834c6f4ce2576d6a064e4

URL: https://github.com/llvm/llvm-project/commit/a5d161c119d5a03c1ce834c6f4ce2576d6a064e4
DIFF: https://github.com/llvm/llvm-project/commit/a5d161c119d5a03c1ce834c6f4ce2576d6a064e4.diff

LOG: [PowerPC] Don't use rldicl for PPC32

According to https://www.ibm.com/support/knowledgecenter/ssw_aix_72/assembler/idalangref_rldicl_rletdw_instrs.html rldicl should not be used when targeting 32bit CPUs.

Reviewed By: #powerpc, nemanjai, MaskRay

Differential Revision: https://reviews.llvm.org/D77946

Added: 
    

Modified: 
    llvm/lib/Target/PowerPC/PPCInstrInfo.td
    llvm/test/CodeGen/PowerPC/testBitReverse.ll

Removed: 
    


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diff  --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index 3db7b25e871d..e40aa727f6dd 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -5068,8 +5068,11 @@ def RotateInsertByte1 {
   dag Left = (RLWIMI RotateInsertByte3.Left, Swap4.Bits, 8, 24, 31);
 }
 
-def : Pat<(i32 (bitreverse i32:$A)),
-  (RLDICL_32 RotateInsertByte1.Left, 0, 32)>;
+// Clear the upper half of the register when in 64-bit mode
+let Predicates = [In64BitMode] in
+def : Pat<(i32 (bitreverse i32:$A)), (RLDICL_32 RotateInsertByte1.Left, 0, 32)>;
+let Predicates = [In32BitMode] in
+def : Pat<(i32 (bitreverse i32:$A)), RotateInsertByte1.Left>;
 
 // Fast 64-bit reverse bits algorithm:
 // Step 1: 1-bit swap (swap odd 1-bit and even 1-bit):

diff  --git a/llvm/test/CodeGen/PowerPC/testBitReverse.ll b/llvm/test/CodeGen/PowerPC/testBitReverse.ll
index d795879a7924..a7c71cd136bb 100644
--- a/llvm/test/CodeGen/PowerPC/testBitReverse.ll
+++ b/llvm/test/CodeGen/PowerPC/testBitReverse.ll
@@ -1,8 +1,43 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -verify-machineinstrs -mtriple=powerpc -mcpu=ppc32 < %s | FileCheck %s --check-prefix=PPC32
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
 ; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
 declare i32 @llvm.bitreverse.i32(i32)
 define i32 @testBitReverseIntrinsicI32(i32 %arg) {
+; PPC32-LABEL: testBitReverseIntrinsicI32:
+; PPC32:       # %bb.0:
+; PPC32-NEXT:    lis 4, -21846
+; PPC32-NEXT:    ori 4, 4, 43690
+; PPC32-NEXT:    slwi 5, 3, 1
+; PPC32-NEXT:    and 4, 5, 4
+; PPC32-NEXT:    lis 5, 21845
+; PPC32-NEXT:    ori 5, 5, 21845
+; PPC32-NEXT:    srwi 3, 3, 1
+; PPC32-NEXT:    and 3, 3, 5
+; PPC32-NEXT:    lis 5, -13108
+; PPC32-NEXT:    or 3, 3, 4
+; PPC32-NEXT:    ori 5, 5, 52428
+; PPC32-NEXT:    slwi 4, 3, 2
+; PPC32-NEXT:    and 4, 4, 5
+; PPC32-NEXT:    lis 5, 13107
+; PPC32-NEXT:    ori 5, 5, 13107
+; PPC32-NEXT:    srwi 3, 3, 2
+; PPC32-NEXT:    and 3, 3, 5
+; PPC32-NEXT:    lis 5, -3856
+; PPC32-NEXT:    or 3, 3, 4
+; PPC32-NEXT:    ori 5, 5, 61680
+; PPC32-NEXT:    slwi 4, 3, 4
+; PPC32-NEXT:    and 4, 4, 5
+; PPC32-NEXT:    lis 5, 3855
+; PPC32-NEXT:    ori 5, 5, 3855
+; PPC32-NEXT:    srwi 3, 3, 4
+; PPC32-NEXT:    and 3, 3, 5
+; PPC32-NEXT:    or 4, 3, 4
+; PPC32-NEXT:    rotlwi 3, 4, 24
+; PPC32-NEXT:    rlwimi 3, 4, 8, 8, 15
+; PPC32-NEXT:    rlwimi 3, 4, 8, 24, 31
+; PPC32-NEXT:    blr
+;
 ; CHECK-LABEL: testBitReverseIntrinsicI32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -21846
@@ -43,6 +78,58 @@ define i32 @testBitReverseIntrinsicI32(i32 %arg) {
 
 declare i64 @llvm.bitreverse.i64(i64)
 define i64 @testBitReverseIntrinsicI64(i64 %arg) {
+; PPC32-LABEL: testBitReverseIntrinsicI64:
+; PPC32:       # %bb.0:
+; PPC32-NEXT:    lis 5, -21846
+; PPC32-NEXT:    lis 6, 21845
+; PPC32-NEXT:    ori 5, 5, 43690
+; PPC32-NEXT:    slwi 10, 4, 1
+; PPC32-NEXT:    slwi 11, 3, 1
+; PPC32-NEXT:    ori 6, 6, 21845
+; PPC32-NEXT:    srwi 4, 4, 1
+; PPC32-NEXT:    srwi 3, 3, 1
+; PPC32-NEXT:    and 10, 10, 5
+; PPC32-NEXT:    and 5, 11, 5
+; PPC32-NEXT:    and 4, 4, 6
+; PPC32-NEXT:    and 3, 3, 6
+; PPC32-NEXT:    lis 7, -13108
+; PPC32-NEXT:    lis 8, 13107
+; PPC32-NEXT:    or 4, 4, 10
+; PPC32-NEXT:    or 3, 3, 5
+; PPC32-NEXT:    ori 7, 7, 52428
+; PPC32-NEXT:    ori 8, 8, 13107
+; PPC32-NEXT:    slwi 5, 4, 2
+; PPC32-NEXT:    srwi 4, 4, 2
+; PPC32-NEXT:    slwi 6, 3, 2
+; PPC32-NEXT:    srwi 3, 3, 2
+; PPC32-NEXT:    and 5, 5, 7
+; PPC32-NEXT:    and 4, 4, 8
+; PPC32-NEXT:    and 6, 6, 7
+; PPC32-NEXT:    and 3, 3, 8
+; PPC32-NEXT:    lis 9, -3856
+; PPC32-NEXT:    lis 11, 3855
+; PPC32-NEXT:    or 4, 4, 5
+; PPC32-NEXT:    or 3, 3, 6
+; PPC32-NEXT:    ori 9, 9, 61680
+; PPC32-NEXT:    ori 11, 11, 3855
+; PPC32-NEXT:    slwi 5, 4, 4
+; PPC32-NEXT:    srwi 4, 4, 4
+; PPC32-NEXT:    slwi 6, 3, 4
+; PPC32-NEXT:    srwi 3, 3, 4
+; PPC32-NEXT:    and 5, 5, 9
+; PPC32-NEXT:    and 4, 4, 11
+; PPC32-NEXT:    and 6, 6, 9
+; PPC32-NEXT:    and 3, 3, 11
+; PPC32-NEXT:    or 5, 4, 5
+; PPC32-NEXT:    or 6, 3, 6
+; PPC32-NEXT:    rotlwi 3, 5, 24
+; PPC32-NEXT:    rotlwi 4, 6, 24
+; PPC32-NEXT:    rlwimi 3, 5, 8, 8, 15
+; PPC32-NEXT:    rlwimi 4, 6, 8, 8, 15
+; PPC32-NEXT:    rlwimi 3, 5, 8, 24, 31
+; PPC32-NEXT:    rlwimi 4, 6, 8, 24, 31
+; PPC32-NEXT:    blr
+;
 ; CHECK-LABEL: testBitReverseIntrinsicI64:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lis 4, -21846