[PATCH] D76445: [WIP][RISCV][GlobalISel] Select ALU GPR instructions

[Lewis Revill via Phabricator via llvm-commits]

lewis-revill updated this revision to Diff 258538.
lewis-revill added a comment.

Bug fix - ensure selectConstant produces copies with fully constrained registers.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D76445/new/

https://reviews.llvm.org/D76445

Files:
  llvm/lib/Target/RISCV/RISCVInstructionSelector.cpp
  llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32.mir
  llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu32_m.mir
  llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64.mir
  llvm/test/CodeGen/RISCV/GlobalISel/instruction-select/alu64_m.mir

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