[PATCH] D78402: [AArch64] Define ACLE FP conversion intrinsics with more specific predicate.

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen created this revision.
sdesmalen added reviewers: efriedma, SjoerdMeijer, paulwalker-arm.
Herald added subscribers: danielkiss, hiraditya, kristof.beyls.
Herald added a reviewer: rengolin.
Herald added a project: clang.
sdesmalen added a parent revision: D78239: [SveEmitter] Add builtins for FP conversions.

This patch changes the FP conversion intrinsics to take a predicate
that matches the number of lanes for the vector with the widest element
type as opposed to using <vscale x 16 x i1>.

For example:

  <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f16(<vscale x 4 x float>, <vscale x 4 x i1>, <vscale x 8 x half>)

now uses <vscale x 4 x i1> instead of <vscale x 16 x i1>

And similar for:

  <vscale x 4 x float> @llvm.aarch64.sve.fcvt.f32f64(<vscale x 4 x float>, <vscale x 2 x i1>, <vscale x 2 x double>)

where the predicate now matches the wider type, so <vscale x 2 x i1>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D78402

Files:
  clang/include/clang/Basic/TargetBuiltins.h
  clang/include/clang/Basic/arm_sve.td
  clang/lib/CodeGen/CGBuiltin.cpp
  clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_cvt.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtlt.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtnt.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtx.c
  clang/test/CodeGen/aarch64-sve2-intrinsics/acle_sve2_cvtxnt.c
  clang/utils/TableGen/SveEmitter.cpp
  llvm/include/llvm/IR/IntrinsicsAArch64.td
  llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
  llvm/lib/Target/AArch64/SVEInstrFormats.td
  llvm/test/CodeGen/AArch64/sve-intrinsics-fp-converts.ll
  llvm/test/CodeGen/AArch64/sve2-intrinsics-fp-converts.ll
  llvm/unittests/IR/IRBuilderTest.cpp

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