[PATCH] D78380: Let the target adjust physical output- and anti-deps
Fraser Cormack via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 17 09:42:43 PDT 2020
frasercrmck created this revision.
frasercrmck added reviewers: foad, MatzeB, rampitec.
frasercrmck added a project: LLVM.
Herald added subscribers: llvm-commits, hiraditya.
This is potentially required by targets for correctness, or at least for optimization purposes.
Let me know what you think. This is necessary for our downstream target as we have a complicated per-operand scheduling model. However, as I don't think it's too controversial I thought I would push it back upstream.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D78380
Files:
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
Index: llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
===================================================================
--- llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -294,6 +294,8 @@
if (MRI.isConstantPhysReg(Reg))
return;
+ const TargetSubtargetInfo &ST = MF.getSubtarget();
+
// Optionally add output and anti dependencies. For anti
// dependencies we use a latency of 0 because for a multi-issue
// target we want to allow the defining instruction to issue
@@ -311,14 +313,12 @@
if (DefSU != SU &&
(Kind != SDep::Output || !MO.isDead() ||
!DefSU->getInstr()->registerDefIsDead(*Alias))) {
- if (Kind == SDep::Anti)
- DefSU->addPred(SDep(SU, Kind, /*Reg=*/*Alias));
- else {
- SDep Dep(SU, Kind, /*Reg=*/*Alias);
+ SDep Dep(SU, Kind, /*Reg=*/*Alias);
+ if (Kind != SDep::Anti)
Dep.setLatency(
SchedModel.computeOutputLatency(MI, OperIdx, DefSU->getInstr()));
- DefSU->addPred(Dep);
- }
+ ST.adjustSchedDependency(SU, OperIdx, DefSU, I->OpIdx, Dep);
+ DefSU->addPred(Dep);
}
}
}
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