[PATCH] D78312: [AMDGPU] Add 192-bit register classes
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Apr 17 02:07:50 PDT 2020
foad updated this revision to Diff 258257.
foad marked an inline comment as done.
foad added a comment.
Update AMDGPURegisterBanks.td.
Add AReg_192 register class.
Remove trailing comma.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D78312/new/
https://reviews.llvm.org/D78312
Files:
llvm/lib/Target/AMDGPU/AMDGPURegisterBanks.td
llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp
llvm/lib/Target/AMDGPU/SIRegisterInfo.td
llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte-xfail.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/cvt_f32_ubyte.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-concat-vectors.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-merge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-unmerge-values.mir
llvm/test/CodeGen/AMDGPU/GlobalISel/zextload-xfail.ll
llvm/test/CodeGen/AMDGPU/GlobalISel/zextload.ll
llvm/test/CodeGen/AMDGPU/ipra-regmask.ll
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