[PATCH] D78278: [CodeGen] Support freeze expand for ppc_fp128

[Zhang Kang via Phabricator via llvm-commits]

ZhangKang updated this revision to Diff 258221.
ZhangKang added a comment.

Rename the case.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78278/new/

https://reviews.llvm.org/D78278

Files:
  llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
  llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
  llvm/test/CodeGen/PowerPC/ppcf128-freeze.mir


Index: llvm/test/CodeGen/PowerPC/ppcf128-freeze.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/ppcf128-freeze.mir
@@ -0,0 +1,35 @@
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -start-after=codegenprepare \
+# RUN:   -o - %s -verify-machineinstrs | FileCheck %s
+
+--- |
+  define ppc_fp128 @freeze_select(ppc_fp128 %a, ppc_fp128 %b) {
+    %sel.frozen = freeze ppc_fp128 %a
+    %cmp = fcmp one ppc_fp128 %sel.frozen, 0xM00000000000000000000000000000000
+    br i1 %cmp, label %select.end, label %select.false
+
+  select.false:                                     ; preds = %0
+    br label %select.end
+
+  select.end:                                       ; preds = %0, %select.false
+    %sel = phi ppc_fp128 [ %a, %0 ], [ %b, %select.false ]
+    ret ppc_fp128 %sel
+  }
+
+  ; CHECK-LABEL: freeze_select
+  ; CHECK:       # %bb.0:
+  ; CHECK-NEXT:    xxlxor 0, 0, 0
+  ; CHECK-NEXT:    fcmpu 5, 2, 2
+  ; CHECK-NEXT:    fcmpu 1, 1, 1
+  ; CHECK-NEXT:    fcmpu 6, 2, 0
+  ; CHECK-NEXT:    fcmpu 0, 1, 0
+  ; CHECK-NEXT:    crnor 20, 23, 26
+  ; CHECK-NEXT:    crand 20, 2, 20
+  ; CHECK-NEXT:    bclr 12, 20, 0
+  ; CHECK-NEXT:  # %bb.1:
+  ; CHECK-NEXT:    crnor 20, 7, 2
+  ; CHECK-NEXT:    bclr 12, 20, 0
+  ; CHECK-NEXT:  # %bb.2:                                # %select.false
+  ; CHECK-NEXT:    fmr 1, 3
+  ; CHECK-NEXT:    fmr 2, 4
+  ; CHECK-NEXT:    blr
+...
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -599,6 +599,7 @@
   void ExpandFloatRes_FP_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandFloatRes_FPOW      (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandFloatRes_FPOWI     (SDNode *N, SDValue &Lo, SDValue &Hi);
+  void ExpandFloatRes_FREEZE    (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandFloatRes_FREM      (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandFloatRes_FRINT     (SDNode *N, SDValue &Lo, SDValue &Hi);
   void ExpandFloatRes_FROUND    (SDNode *N, SDValue &Lo, SDValue &Hi);
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -1173,6 +1173,7 @@
   case ISD::FPOW:       ExpandFloatRes_FPOW(N, Lo, Hi); break;
   case ISD::STRICT_FPOWI:
   case ISD::FPOWI:      ExpandFloatRes_FPOWI(N, Lo, Hi); break;
+  case ISD::FREEZE:     ExpandFloatRes_FREEZE(N, Lo, Hi); break;
   case ISD::STRICT_FRINT:
   case ISD::FRINT:      ExpandFloatRes_FRINT(N, Lo, Hi); break;
   case ISD::STRICT_FROUND:
@@ -1466,6 +1467,17 @@
                                         RTLIB::POWI_PPCF128), Lo, Hi);
 }
 
+void DAGTypeLegalizer::ExpandFloatRes_FREEZE(SDNode *N,
+                                             SDValue &Lo, SDValue &Hi) {
+  assert(N->getValueType(0) == MVT::ppcf128 &&
+         "Logic only correct for ppcf128!");
+
+  SDLoc dl(N);
+  GetExpandedFloat(N->getOperand(0), Lo, Hi);
+  Lo = DAG.getNode(ISD::FREEZE, dl, Lo.getValueType(), Lo);
+  Hi = DAG.getNode(ISD::FREEZE, dl, Hi.getValueType(), Hi);
+}
+
 void DAGTypeLegalizer::ExpandFloatRes_FREM(SDNode *N,
                                            SDValue &Lo, SDValue &Hi) {
   ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),


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