[PATCH] D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:3698
+                                            ? MRI.getRegClass(Src1.getReg())
+                                            : &AMDGPU::VGPR_32RegClass;
+    const TargetRegisterClass *Src0SubRC =
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alex-t wrote:
> rampitec wrote:
> > VReg_64? Since it did not fail anywhere this case must be not covered by any tests.
> I maybe misunderstand the documentation, but it says that the size we only can have 32bit immediate aa operand.
> I also did some experiments with different targets (gfx600,900,1010) and always have seen that 64bit size constant was split into 2 32bit parts for addition.
> Please correct me if I understand it in a wrong way.
Two lines below you are asking for sub0 of that RC. VGPR_32 does not have sub0.


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  https://reviews.llvm.org/D78091/new/

https://reviews.llvm.org/D78091