[PATCH] D77435: [llvm][CodeGen] Addressing modes for SVE stN.

[Francesco Petrogalli via Phabricator via llvm-commits]

fpetrogalli marked 5 inline comments as done.
fpetrogalli added inline comments.


================
Comment at: llvm/test/CodeGen/AArch64/sve-intrinsics-stN-reg-imm-addr-mode.ll:246
+; CHECK-LABEL: st3b_i8_valid_imm_lower_bound:
+; CHECK:      st3b { z0.b, z1.b, z2.b }, p0, [x0, #-24, mul vl]
+; CHECK-NEXT: ret
----------------
c-rhodes wrote:
> fpetrogalli wrote:
> > c-rhodes wrote:
> > > nit: formatting
> > Not sure what you want me to do here.
> I don't think I do either :D
> 
> I noticed in the valid upper/lower bound tests you have:
> ```; CHECK:      st3b { z0.b, z1.b, z2.b }, p0, [x0, #-24, mul vl]
> ; CHECK-NEXT: ret```
> 
> and others (e.g. `st3h_i16`):
> ```; CHECK: st3h { z0.h, z1.h, z2.h }, p0, [x0, #6, mul vl]
> ; CHECK-NEXT: ret```
> 
> but I know that wasn't what I meant yesterday, feel free to ignore this.
> 
I have removed all multiple spaces after the `CHECK*:`.


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  https://reviews.llvm.org/D77435/new/

https://reviews.llvm.org/D77435