[llvm] 1a3e89a - [MIR] Add comments to INLINEASM immediate flag MachineOperands
Konstantin Schwarz via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 16 04:48:03 PDT 2020
Author: Konstantin Schwarz
Date: 2020-04-16T13:46:14+02:00
New Revision: 1a3e89aa2bd26ad05b25635457bad28f46427eeb
URL: https://github.com/llvm/llvm-project/commit/1a3e89aa2bd26ad05b25635457bad28f46427eeb
DIFF: https://github.com/llvm/llvm-project/commit/1a3e89aa2bd26ad05b25635457bad28f46427eeb.diff
LOG: [MIR] Add comments to INLINEASM immediate flag MachineOperands
Summary:
The INLINEASM MIR instructions use immediate operands to encode the values of some operands.
The MachineInstr pretty printer function already handles those operands and prints human readable annotations instead of the immediates. This patch adds similar annotations to the output of the MIRPrinter, however uses the new MIROperandComment feature.
Reviewers: SjoerdMeijer, arsenm, efriedma
Reviewed By: arsenm
Subscribers: qcolombet, sdardis, jvesely, wdng, nhaehnle, hiraditya, jrtc27, atanasyan, kerbowa, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D78088
Added:
Modified:
llvm/include/llvm/CodeGen/TargetInstrInfo.h
llvm/include/llvm/IR/InlineAsm.h
llvm/lib/CodeGen/MIRPrinter.cpp
llvm/lib/CodeGen/MachineInstr.cpp
llvm/lib/CodeGen/TargetInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
llvm/lib/Target/ARM/ARMBaseInstrInfo.h
llvm/test/CodeGen/AArch64/seqpairspill.mir
llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
llvm/test/CodeGen/Thumb2/high-reg-spill.mir
llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll
llvm/test/CodeGen/X86/stack-folding-adx.mir
llvm/test/CodeGen/X86/stack-folding-bmi2.mir
llvm/test/CodeGen/X86/stack-folding-fp-nofpexcept.mir
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index 58ea804d2747..7792738f4ec9 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -1310,11 +1310,9 @@ class TargetInstrInfo : public MCInstrInfo {
virtual bool isPredicated(const MachineInstr &MI) const { return false; }
// Returns a MIRPrinter comment for this machine operand.
- virtual std::string createMIROperandComment(const MachineInstr &MI,
- const MachineOperand &Op,
- unsigned OpIdx) const {
- return std::string();
- };
+ virtual std::string
+ createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
+ unsigned OpIdx, const TargetRegisterInfo *TRI) const;
/// Returns true if the instruction is a
/// terminator instruction that has not been predicated.
diff --git a/llvm/include/llvm/IR/InlineAsm.h b/llvm/include/llvm/IR/InlineAsm.h
index 72d8ad1501ae..b6f377093337 100644
--- a/llvm/include/llvm/IR/InlineAsm.h
+++ b/llvm/include/llvm/IR/InlineAsm.h
@@ -17,6 +17,7 @@
#include "llvm/ADT/StringRef.h"
#include "llvm/IR/Value.h"
+#include "llvm/Support/ErrorHandling.h"
#include <cassert>
#include <string>
#include <vector>
@@ -359,6 +360,96 @@ class InlineAsm final : public Value {
RC = High - 1;
return true;
}
+
+ static std::vector<StringRef> getExtraInfoNames(unsigned ExtraInfo) {
+ std::vector<StringRef> Result;
+ if (ExtraInfo & InlineAsm::Extra_HasSideEffects)
+ Result.push_back("sideeffect");
+ if (ExtraInfo & InlineAsm::Extra_MayLoad)
+ Result.push_back("mayload");
+ if (ExtraInfo & InlineAsm::Extra_MayStore)
+ Result.push_back("maystore");
+ if (ExtraInfo & InlineAsm::Extra_IsConvergent)
+ Result.push_back("isconvergent");
+ if (ExtraInfo & InlineAsm::Extra_IsAlignStack)
+ Result.push_back("alignstack");
+
+ AsmDialect Dialect =
+ InlineAsm::AsmDialect((ExtraInfo & InlineAsm::Extra_AsmDialect));
+
+ if (Dialect == InlineAsm::AD_ATT)
+ Result.push_back("attdialect");
+ if (Dialect == InlineAsm::AD_Intel)
+ Result.push_back("inteldialect");
+
+ return Result;
+ }
+
+ static StringRef getKindName(unsigned Kind) {
+ switch (Kind) {
+ case InlineAsm::Kind_RegUse:
+ return "reguse";
+ case InlineAsm::Kind_RegDef:
+ return "regdef";
+ case InlineAsm::Kind_RegDefEarlyClobber:
+ return "regdef-ec";
+ case InlineAsm::Kind_Clobber:
+ return "clobber";
+ case InlineAsm::Kind_Imm:
+ return "imm";
+ case InlineAsm::Kind_Mem:
+ return "mem";
+ default:
+ llvm_unreachable("Unknown operand kind");
+ }
+ }
+
+ static StringRef getMemConstraintName(unsigned Constraint) {
+ switch (Constraint) {
+ case InlineAsm::Constraint_es:
+ return "es";
+ case InlineAsm::Constraint_i:
+ return "i";
+ case InlineAsm::Constraint_m:
+ return "m";
+ case InlineAsm::Constraint_o:
+ return "o";
+ case InlineAsm::Constraint_v:
+ return "v";
+ case InlineAsm::Constraint_Q:
+ return "Q";
+ case InlineAsm::Constraint_R:
+ return "R";
+ case InlineAsm::Constraint_S:
+ return "S";
+ case InlineAsm::Constraint_T:
+ return "T";
+ case InlineAsm::Constraint_Um:
+ return "Um";
+ case InlineAsm::Constraint_Un:
+ return "Un";
+ case InlineAsm::Constraint_Uq:
+ return "Uq";
+ case InlineAsm::Constraint_Us:
+ return "Us";
+ case InlineAsm::Constraint_Ut:
+ return "Ut";
+ case InlineAsm::Constraint_Uv:
+ return "Uv";
+ case InlineAsm::Constraint_Uy:
+ return "Uy";
+ case InlineAsm::Constraint_X:
+ return "X";
+ case InlineAsm::Constraint_Z:
+ return "Z";
+ case InlineAsm::Constraint_ZC:
+ return "ZC";
+ case InlineAsm::Constraint_Zy:
+ return "Zy";
+ default:
+ llvm_unreachable("Unknown memory constraint");
+ }
+ }
};
} // end namespace llvm
diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp
index 550448027915..5e01af25bdd8 100644
--- a/llvm/lib/CodeGen/MIRPrinter.cpp
+++ b/llvm/lib/CodeGen/MIRPrinter.cpp
@@ -860,7 +860,7 @@ void MIPrinter::print(const MachineInstr &MI, unsigned OpIdx,
bool ShouldPrintRegisterTies, LLT TypeToPrint,
bool PrintDef) {
const MachineOperand &Op = MI.getOperand(OpIdx);
- std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx);
+ std::string MOComment = TII->createMIROperandComment(MI, Op, OpIdx, TRI);
switch (Op.getType()) {
case MachineOperand::MO_Immediate:
diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp
index 542dc220ad30..8ee85c6229b6 100644
--- a/llvm/lib/CodeGen/MachineInstr.cpp
+++ b/llvm/lib/CodeGen/MachineInstr.cpp
@@ -1669,15 +1669,8 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
// Pretty print the inline asm operand descriptor.
OS << '$' << AsmOpCount++;
unsigned Flag = MO.getImm();
- switch (InlineAsm::getKind(Flag)) {
- case InlineAsm::Kind_RegUse: OS << ":[reguse"; break;
- case InlineAsm::Kind_RegDef: OS << ":[regdef"; break;
- case InlineAsm::Kind_RegDefEarlyClobber: OS << ":[regdef-ec"; break;
- case InlineAsm::Kind_Clobber: OS << ":[clobber"; break;
- case InlineAsm::Kind_Imm: OS << ":[imm"; break;
- case InlineAsm::Kind_Mem: OS << ":[mem"; break;
- default: OS << ":[??" << InlineAsm::getKind(Flag); break;
- }
+ OS << ":[";
+ OS << InlineAsm::getKindName(InlineAsm::getKind(Flag));
unsigned RCID = 0;
if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
@@ -1690,29 +1683,7 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST,
if (InlineAsm::isMemKind(Flag)) {
unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
- switch (MCID) {
- case InlineAsm::Constraint_es: OS << ":es"; break;
- case InlineAsm::Constraint_i: OS << ":i"; break;
- case InlineAsm::Constraint_m: OS << ":m"; break;
- case InlineAsm::Constraint_o: OS << ":o"; break;
- case InlineAsm::Constraint_v: OS << ":v"; break;
- case InlineAsm::Constraint_Q: OS << ":Q"; break;
- case InlineAsm::Constraint_R: OS << ":R"; break;
- case InlineAsm::Constraint_S: OS << ":S"; break;
- case InlineAsm::Constraint_T: OS << ":T"; break;
- case InlineAsm::Constraint_Um: OS << ":Um"; break;
- case InlineAsm::Constraint_Un: OS << ":Un"; break;
- case InlineAsm::Constraint_Uq: OS << ":Uq"; break;
- case InlineAsm::Constraint_Us: OS << ":Us"; break;
- case InlineAsm::Constraint_Ut: OS << ":Ut"; break;
- case InlineAsm::Constraint_Uv: OS << ":Uv"; break;
- case InlineAsm::Constraint_Uy: OS << ":Uy"; break;
- case InlineAsm::Constraint_X: OS << ":X"; break;
- case InlineAsm::Constraint_Z: OS << ":Z"; break;
- case InlineAsm::Constraint_ZC: OS << ":ZC"; break;
- case InlineAsm::Constraint_Zy: OS << ":Zy"; break;
- default: OS << ":?"; break;
- }
+ OS << ":" << InlineAsm::getMemConstraintName(MCID);
}
unsigned TiedTo = 0;
diff --git a/llvm/lib/CodeGen/TargetInstrInfo.cpp b/llvm/lib/CodeGen/TargetInstrInfo.cpp
index 2e515094cf6c..0c91cc166f57 100644
--- a/llvm/lib/CodeGen/TargetInstrInfo.cpp
+++ b/llvm/lib/CodeGen/TargetInstrInfo.cpp
@@ -1322,4 +1322,60 @@ bool TargetInstrInfo::getInsertSubregInputs(
return true;
}
+// Returns a MIRPrinter comment for this machine operand.
+std::string TargetInstrInfo::createMIROperandComment(
+ const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
+ const TargetRegisterInfo *TRI) const {
+
+ if (!MI.isInlineAsm())
+ return "";
+
+ std::string Flags;
+ raw_string_ostream OS(Flags);
+
+ if (OpIdx == InlineAsm::MIOp_ExtraInfo) {
+ // Print HasSideEffects, MayLoad, MayStore, IsAlignStack
+ unsigned ExtraInfo = Op.getImm();
+ bool First = true;
+ for (StringRef Info : InlineAsm::getExtraInfoNames(ExtraInfo)) {
+ if (!First)
+ OS << " ";
+ First = false;
+ OS << Info;
+ }
+
+ return OS.str();
+ }
+
+ int FlagIdx = MI.findInlineAsmFlagIdx(OpIdx);
+ if (FlagIdx < 0 || (unsigned)FlagIdx != OpIdx)
+ return "";
+
+ assert(Op.isImm() && "Expected flag operand to be an immediate");
+ // Pretty print the inline asm operand descriptor.
+ unsigned Flag = Op.getImm();
+ unsigned Kind = InlineAsm::getKind(Flag);
+ OS << InlineAsm::getKindName(Kind);
+
+ unsigned RCID = 0;
+ if (!InlineAsm::isImmKind(Flag) && !InlineAsm::isMemKind(Flag) &&
+ InlineAsm::hasRegClassConstraint(Flag, RCID)) {
+ if (TRI) {
+ OS << ':' << TRI->getRegClassName(TRI->getRegClass(RCID));
+ } else
+ OS << ":RC" << RCID;
+ }
+
+ if (InlineAsm::isMemKind(Flag)) {
+ unsigned MCID = InlineAsm::getMemoryConstraintID(Flag);
+ OS << ":" << InlineAsm::getMemConstraintName(MCID);
+ }
+
+ unsigned TiedTo = 0;
+ if (InlineAsm::isUseOperandTiedToDef(Flag, TiedTo))
+ OS << " tiedto:$" << TiedTo;
+
+ return OS.str();
+}
+
TargetInstrInfo::PipelinerLoopInfo::~PipelinerLoopInfo() {}
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
index fc4e7182bf11..63bea53a72fa 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -495,10 +495,17 @@ bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const {
return PIdx != -1 && MI.getOperand(PIdx).getImm() != ARMCC::AL;
}
-std::string ARMBaseInstrInfo::createMIROperandComment(const MachineInstr &MI,
- const MachineOperand &Op,
- unsigned OpIdx) const {
- // Only support immediates for now.
+std::string ARMBaseInstrInfo::createMIROperandComment(
+ const MachineInstr &MI, const MachineOperand &Op, unsigned OpIdx,
+ const TargetRegisterInfo *TRI) const {
+
+ // First, let's see if there is a generic comment for this operand
+ std::string GenericComment =
+ TargetInstrInfo::createMIROperandComment(MI, Op, OpIdx, TRI);
+ if (!GenericComment.empty())
+ return GenericComment;
+
+ // If not, check if we have an immediate operand.
if (Op.getType() != MachineOperand::MO_Immediate)
return std::string();
diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
index 9f23483e595c..173b57c62a2f 100644
--- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
+++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.h
@@ -152,9 +152,10 @@ class ARMBaseInstrInfo : public ARMGenInstrInfo {
bool isPredicated(const MachineInstr &MI) const override;
// MIR printer helper function to annotate Operands with a comment.
- std::string createMIROperandComment(const MachineInstr &MI,
- const MachineOperand &Op,
- unsigned OpIdx) const override;
+ std::string
+ createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,
+ unsigned OpIdx,
+ const TargetRegisterInfo *TRI) const override;
ARMCC::CondCodes getPredicate(const MachineInstr &MI) const {
int PIdx = MI.findFirstPredOperandIdx();
diff --git a/llvm/test/CodeGen/AArch64/seqpairspill.mir b/llvm/test/CodeGen/AArch64/seqpairspill.mir
index fdcb3dc61181..12748378e678 100644
--- a/llvm/test/CodeGen/AArch64/seqpairspill.mir
+++ b/llvm/test/CodeGen/AArch64/seqpairspill.mir
@@ -16,7 +16,7 @@ body: |
%1 : xseqpairsclass = IMPLICIT_DEF
%2 : gpr64common = IMPLICIT_DEF
%0 = CASPALX %0, %1, %2
- INLINEASM &" ", 0, 0, implicit def dead $x0, implicit def dead $x1, implicit def dead $x2, implicit def dead $x3, implicit def dead $x4, implicit def dead $x5, implicit def dead $x6, implicit def dead $x7, implicit def dead $x8, implicit def dead $x9, implicit def dead $x10, implicit def dead $x11, implicit def dead $x12, implicit def dead $x13, implicit def dead $x14, implicit def dead $x15, implicit def dead $x16, implicit def dead $x17, implicit def dead $x18, implicit def dead $x19, implicit def dead $x20, implicit def dead $x21, implicit def dead $x22, implicit def dead $x23, implicit def dead $x24, implicit def dead $x25, implicit def dead $x26, implicit def dead $x27, implicit def dead $x28, implicit def dead $fp, implicit def dead $lr
+ INLINEASM &" ", 0, 12, implicit def dead $x0, implicit def dead $x1, implicit def dead $x2, implicit def dead $x3, implicit def dead $x4, implicit def dead $x5, implicit def dead $x6, implicit def dead $x7, implicit def dead $x8, implicit def dead $x9, implicit def dead $x10, implicit def dead $x11, implicit def dead $x12, implicit def dead $x13, implicit def dead $x14, implicit def dead $x15, implicit def dead $x16, implicit def dead $x17, implicit def dead $x18, implicit def dead $x19, implicit def dead $x20, implicit def dead $x21, implicit def dead $x22, implicit def dead $x23, implicit def dead $x24, implicit def dead $x25, implicit def dead $x26, implicit def dead $x27, implicit def dead $x28, implicit def dead $fp, implicit def dead $lr
$xzr = COPY %0.sube64
$xzr = COPY %0.subo64
...
@@ -36,7 +36,7 @@ body: |
%1 : wseqpairsclass = IMPLICIT_DEF
%2 : gpr64common = IMPLICIT_DEF
%0 = CASPALW %0, %1, %2
- INLINEASM &" ", 0, 0, implicit def dead $x0, implicit def dead $x1, implicit def dead $x2, implicit def dead $x3, implicit def dead $x4, implicit def dead $x5, implicit def dead $x6, implicit def dead $x7, implicit def dead $x8, implicit def dead $x9, implicit def dead $x10, implicit def dead $x11, implicit def dead $x12, implicit def dead $x13, implicit def dead $x14, implicit def dead $x15, implicit def dead $x16, implicit def dead $x17, implicit def dead $x18, implicit def dead $x19, implicit def dead $x20, implicit def dead $x21, implicit def dead $x22, implicit def dead $x23, implicit def dead $x24, implicit def dead $x25, implicit def dead $x26, implicit def dead $x27, implicit def dead $x28, implicit def dead $fp, implicit def dead $lr
+ INLINEASM &" ", 0, 12, implicit def dead $x0, implicit def dead $x1, implicit def dead $x2, implicit def dead $x3, implicit def dead $x4, implicit def dead $x5, implicit def dead $x6, implicit def dead $x7, implicit def dead $x8, implicit def dead $x9, implicit def dead $x10, implicit def dead $x11, implicit def dead $x12, implicit def dead $x13, implicit def dead $x14, implicit def dead $x15, implicit def dead $x16, implicit def dead $x17, implicit def dead $x18, implicit def dead $x19, implicit def dead $x20, implicit def dead $x21, implicit def dead $x22, implicit def dead $x23, implicit def dead $x24, implicit def dead $x25, implicit def dead $x26, implicit def dead $x27, implicit def dead $x28, implicit def dead $fp, implicit def dead $lr
$xzr = COPY %0.sube32
$xzr = COPY %0.subo32
...
diff --git a/llvm/test/CodeGen/AMDGPU/endpgm-dce.mir b/llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
index 7733b0487cf7..baa54b492f61 100644
--- a/llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
+++ b/llvm/test/CodeGen/AMDGPU/endpgm-dce.mir
@@ -331,7 +331,7 @@ body: |
%1 = IMPLICIT_DEF
$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
%2:sreg_64 = IMPLICIT_DEF
- INLINEASM &"", 0, 0
+ INLINEASM &"", 0
S_ENDPGM 0
...
@@ -353,6 +353,6 @@ body: |
%1 = IMPLICIT_DEF
$sgpr0_sgpr1 = S_OR_B64 $exec, killed $vcc, implicit-def $scc
%2:sreg_64 = IMPLICIT_DEF
- INLINEASM &"", 1, 0
+ INLINEASM &"", 1
S_ENDPGM 0
...
diff --git a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
index 789b15556455..134b2a0fb589 100644
--- a/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
+++ b/llvm/test/CodeGen/AMDGPU/rename-independent-subregs.mir
@@ -73,7 +73,7 @@ body: |
# (1) %0.sub0 + %0.sub0 and (2) %0.sub1 + %0.sub1
# Check that renaming (2) does not inadvertently rename (1).
# CHECK-LABEL: name: test2
-# CHECK: INLINEASM &"", 32, 327690, def undef %0.sub0, 327690, def dead %1.sub1, 2147483657, undef %0.sub0(tied-def 3), 2147549193, %1.sub1(tied-def 5)
+# CHECK: INLINEASM &"", 32 /* isconvergent attdialect */, 327690 /* regdef:SReg_1_XEXEC_with_sub0 */, def undef %0.sub0, 327690 /* regdef:SReg_1_XEXEC_with_sub0 */, def dead %1.sub1, 2147483657 /* reguse tiedto:$0 */, undef %0.sub0(tied-def 3), 2147549193 /* reguse tiedto:$1 */, %1.sub1(tied-def 5)
name: test2
body: |
bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir b/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
index e12cff942bc6..53c4544c0bf9 100644
--- a/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
+++ b/llvm/test/CodeGen/AMDGPU/sched-assert-dead-def-subreg-use-other-subreg.mir
@@ -33,7 +33,7 @@ body: |
; CHECK: dead %9:vreg_128 = DS_READ_B128_gfx9 [[V_ADD_U32_e32_]], 0, 0, implicit $exec
; CHECK: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0
; CHECK: undef %11.sub1:vreg_512 = COPY [[COPY]].sub1
- ; CHECK: INLINEASM &"", 1, 851978, def dead [[COPY1]], 851978, def dead [[COPY]].sub1, 2147483657, [[COPY1]], 2147549193, [[COPY]].sub1
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def dead [[COPY1]], 851978 /* regdef:VRegOrLds_32 */, def dead [[COPY]].sub1, 2147483657 /* reguse tiedto:$0 */, [[COPY1]], 2147549193 /* reguse tiedto:$1 */, [[COPY]].sub1
; CHECK: %11.sub0:vreg_512 = COPY [[COPY]].sub0
; CHECK: %11.sub3:vreg_512 = COPY [[COPY]].sub3
; CHECK: dead %10:vgpr_32 = V_ADD_I32_e32 4, [[V_MOV_B32_e32_1]], implicit-def dead $vcc, implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir b/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
index bd0423c5457c..f43289ffee2a 100644
--- a/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
+++ b/llvm/test/CodeGen/AMDGPU/sched-handleMoveUp-subreg-def-across-subreg-def.mir
@@ -36,18 +36,18 @@ body: |
; CHECK: [[DEF2:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
; CHECK: bb.1:
; CHECK: successors: %bb.1(0x80000000)
- ; CHECK: INLINEASM &"", 1, 851978, def dead %11
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def dead %11
; CHECK: GLOBAL_STORE_DWORD undef %12:vreg_64, [[BUFFER_LOAD_DWORD_OFFEN]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; CHECK: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK: [[V_MOV_B32_e32_3:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
; CHECK: [[DS_READ_B64_gfx9_:%[0-9]+]]:vreg_64 = DS_READ_B64_gfx9 undef %14:vgpr_32, 0, 0, implicit $exec :: (load 8, addrspace 3)
- ; CHECK: INLINEASM &"def $0 $1", 1, 851978, def %15, 851978, def %16
+ ; CHECK: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def %15, 851978 /* regdef:VRegOrLds_32 */, def %16
; CHECK: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec
; CHECK: [[DS_READ_B32_gfx9_1:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec
; CHECK: [[DS_READ_B32_gfx9_2:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 undef %20:vgpr_32, 0, 0, implicit $exec
- ; CHECK: INLINEASM &"def $0 $1", 1, 851978, def %21, 851978, def %22
+ ; CHECK: INLINEASM &"def $0 $1", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def %21, 851978 /* regdef:VRegOrLds_32 */, def %22
; CHECK: [[DS_READ_B32_gfx9_3:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_1]], 0, 0, implicit $exec
- ; CHECK: INLINEASM &"", 1, 851978, def dead [[V_MOV_B32_e32_2]], 851978, def dead [[V_MOV_B32_e32_3]], 851977, [[DS_READ_B64_gfx9_]].sub0, 2147483657, [[V_MOV_B32_e32_2]](tied-def 3), 2147549193, [[V_MOV_B32_e32_3]](tied-def 5), 851977, %15, 851977, %16, 851977, [[DS_READ_B32_gfx9_1]], 851977, [[DS_READ_B32_gfx9_]], 851977, [[DS_READ_B32_gfx9_3]], 851977, [[DS_READ_B32_gfx9_2]]
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def dead [[V_MOV_B32_e32_2]], 851978 /* regdef:VRegOrLds_32 */, def dead [[V_MOV_B32_e32_3]], 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B64_gfx9_]].sub0, 2147483657 /* reguse tiedto:$0 */, [[V_MOV_B32_e32_2]](tied-def 3), 2147549193 /* reguse tiedto:$1 */, [[V_MOV_B32_e32_3]](tied-def 5), 851977 /* reguse:VRegOrLds_32 */, %15, 851977 /* reguse:VRegOrLds_32 */, %16, 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_1]], 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_]], 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_3]], 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_2]]
; CHECK: %5.sub1:vreg_64 = COPY [[V_MOV_B32_e32_]]
; CHECK: DS_WRITE_B32_gfx9 undef %28:vgpr_32, %21, 0, 0, implicit $exec :: (store 4, addrspace 3)
; CHECK: DS_WRITE_B32_gfx9 undef %29:vgpr_32, %22, 0, 0, implicit $exec :: (store 4, addrspace 3)
@@ -69,7 +69,7 @@ body: |
; CHECK: undef %42.sub0:sgpr_64 = V_READFIRSTLANE_B32 %38.sub0, implicit $exec
; CHECK: %42.sub1:sgpr_64 = V_READFIRSTLANE_B32 %40.sub1, implicit $exec
; CHECK: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %42, 0, 0, 0 :: (load 4, addrspace 1)
- ; CHECK: INLINEASM &"", 1
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */
; CHECK: [[DS_READ_B32_gfx9_4:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 undef %45:vgpr_32, 0, 0, implicit $exec :: (load 4, addrspace 3)
; CHECK: GLOBAL_STORE_DWORD undef %46:vreg_64, [[DS_READ_B32_gfx9_4]], 0, 0, 0, 0, implicit $exec :: (store 4, addrspace 1)
; CHECK: %31.sub0:vreg_64 = COPY [[S_LOAD_DWORD_IMM]], implicit $exec
diff --git a/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir b/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
index 3a574977e4d8..522f9a0385c6 100644
--- a/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
+++ b/llvm/test/CodeGen/AMDGPU/subreg-undef-def-with-other-subreg-defs.mir
@@ -25,9 +25,9 @@ body: |
; CHECK: bb.1:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load 4, addrspace 3)
- ; CHECK: INLINEASM &"", 1, 851978, def %0, 2147549193, %0(tied-def 3)
- ; CHECK: INLINEASM &"", 1, 851977, [[DS_READ_B32_gfx9_]]
- ; CHECK: INLINEASM &"", 1, 851978, def undef %0.sub0, 851978, def undef %0.sub1
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_]]
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def undef %0.sub0, 851978 /* regdef:VRegOrLds_32 */, def undef %0.sub1
; CHECK: S_NOP 0, implicit %0.sub1
; CHECK: $sgpr10 = S_MOV_B32 -1
; CHECK: S_BRANCH %bb.1
@@ -63,9 +63,9 @@ body: |
; CHECK: bb.1:
; CHECK: successors: %bb.1(0x80000000)
; CHECK: [[DS_READ_B32_gfx9_:%[0-9]+]]:vgpr_32 = DS_READ_B32_gfx9 [[V_MOV_B32_e32_]], 0, 0, implicit $exec :: (load 4, addrspace 3)
- ; CHECK: INLINEASM &"", 1, 851978, def %0, 2147549193, %0(tied-def 3)
- ; CHECK: INLINEASM &"", 1, 851977, [[DS_READ_B32_gfx9_]]
- ; CHECK: INLINEASM &"", 1, 851978, def undef %0.sub1, 851978, def undef %0.sub0
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def %0, 2147549193 /* reguse tiedto:$1 */, %0(tied-def 3)
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851977 /* reguse:VRegOrLds_32 */, [[DS_READ_B32_gfx9_]]
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 851978 /* regdef:VRegOrLds_32 */, def undef %0.sub1, 851978 /* regdef:VRegOrLds_32 */, def undef %0.sub0
; CHECK: S_NOP 0, implicit %0.sub1
; CHECK: $sgpr10 = S_MOV_B32 -1
; CHECK: S_BRANCH %bb.1
diff --git a/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir b/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
index 686ff6f3b0c9..20c21aae6c75 100644
--- a/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
+++ b/llvm/test/CodeGen/AMDGPU/vccz-corrupt-bug-workaround.mir
@@ -134,7 +134,7 @@ body: |
# instructions to fix vccz.
# CHECK-LABEL: name: inlineasm_def_vcc_lo
-# CHECK: INLINEASM &"; def vcc_lo", 1, 10, implicit-def $vcc_lo
+# CHECK: INLINEASM &"; def vcc_lo", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vcc_lo
# SI: $vcc = S_MOV_B64 $vcc
# GFX9: $vcc = S_MOV_B64 $vcc
# CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
@@ -152,7 +152,7 @@ body: |
# inserted to fix vccz.
# CHECK-LABEL: name: inlineasm_def_vcc
-# CHECK: INLINEASM &"; def vcc", 1, 10, implicit-def $vcc
+# CHECK: INLINEASM &"; def vcc", 1 /* sideeffect attdialect */, 10 /* regdef */, implicit-def $vcc
# CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc
name: inlineasm_def_vcc
diff --git a/llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir b/llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
index 466cf6a9862c..227544961b2a 100644
--- a/llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
+++ b/llvm/test/CodeGen/ARM/ifcvt-diamond-unanalyzable-common.mir
@@ -26,10 +26,10 @@ body: |
; CHECK: $r0 = t2MOVi 2, 1 /* CC::ne */, $cpsr, $noreg
; CHECK: $r0 = t2MOVi 3, 0 /* CC::eq */, killed $cpsr, $noreg, implicit killed $r0
; CHECK: tBL 14 /* CC::al */, $noreg, @fn2, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit killed $r1, implicit-def $sp, implicit-def dead $r0
- ; CHECK: INLINEASM_BR &"", 9, 13, 0, 13, blockaddress(@fn1, %ir-block.l_yes)
+ ; CHECK: INLINEASM_BR &"", 9 /* sideeffect mayload attdialect */, 13 /* imm */, 0, 13 /* imm */, blockaddress(@fn1, %ir-block.l_yes)
; CHECK: t2B %bb.1, 14 /* CC::al */, $noreg
; CHECK: bb.1:
- ; CHECK: INLINEASM &"", 1
+ ; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */
; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
; CHECK: bb.2.l_yes (address-taken):
; CHECK: $sp = t2LDMIA_RET $sp, 14 /* CC::al */, $noreg, def $r4, def $pc
diff --git a/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir b/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
index 3829489e2a9a..87ea82623ee9 100644
--- a/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
+++ b/llvm/test/CodeGen/MIR/X86/early-clobber-register-flag.mir
@@ -35,7 +35,7 @@ body: |
CFI_INSTRUCTION def_cfa_offset 16
$ecx = COPY $edi
$ecx = ADD32rr killed $ecx, killed $esi, implicit-def dead $eflags
- ; CHECK: INLINEASM &nop, 1, 12, implicit-def dead early-clobber $ax, 12, implicit-def dead early-clobber $di
+ ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $ax, 12 /* clobber */, implicit-def dead early-clobber $di
INLINEASM &nop, 1, 12, implicit-def dead early-clobber $ax, 12, implicit-def dead early-clobber $di
$edi = COPY killed $ecx
CALL64pcrel32 @foo, csr_64, implicit $rsp, implicit $edi, implicit-def $rsp
diff --git a/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir b/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
index 3403ac867379..fd1e7aaa3209 100644
--- a/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
+++ b/llvm/test/CodeGen/MIR/X86/inline-asm-registers.mir
@@ -28,7 +28,7 @@ body: |
liveins: $rdi, $rsi
; CHECK-LABEL: name: test
- ; CHECK: INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi,
+ ; CHECK: INLINEASM &foo, 0 /* attdialect */, 2818058 /* regdef:GR32_TC */, def $rsi, 2818058 /* regdef:GR32_TC */, def dead $rdi,
INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi, 2147549193, killed $rdi, 2147483657, killed $rsi, 12, implicit-def dead early-clobber $eflags
$rax = MOV64rr killed $rsi
RETQ killed $rax
@@ -45,7 +45,7 @@ body: |
; Verify that the register ties are preserved.
; CHECK-LABEL: name: test2
- ; CHECK: INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi, 2147549193, killed $rdi(tied-def 5), 2147483657, killed $rsi(tied-def 3), 12, implicit-def dead early-clobber $eflags
+ ; CHECK: INLINEASM &foo, 0 /* attdialect */, 2818058 /* regdef:GR32_TC */, def $rsi, 2818058 /* regdef:GR32_TC */, def dead $rdi, 2147549193 /* reguse tiedto:$1 */, killed $rdi(tied-def 5), 2147483657 /* reguse tiedto:$0 */, killed $rsi(tied-def 3), 12 /* clobber */, implicit-def dead early-clobber $eflags
INLINEASM &foo, 0, 2818058, def $rsi, 2818058, def dead $rdi, 2147549193, killed $rdi(tied-def 5), 2147483657, killed $rsi(tied-def 3), 12, implicit-def dead early-clobber $eflags
$rax = MOV64rr killed $rsi
RETQ killed $rax
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
index 2411f65b1758..7224d0ddc5ff 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromips.mir
@@ -81,7 +81,7 @@ body: |
; MM: NOP
; MM: }
; MM: bb.2.if.then:
- ; MM: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; MM: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MM: $v0 = LI16_MM 0
; MM: JRC16_MM undef $ra, implicit killed $v0
; MM: bb.3.return:
@@ -110,7 +110,7 @@ body: |
; PIC: $sp = ADDiu $sp, 8
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: $v0 = LI16_MM 0
; PIC: JRC16_MM undef $ra, implicit killed $v0
; PIC: bb.4.return:
@@ -179,7 +179,7 @@ body: |
; MM: $v0 = LI16_MM 1
; MM: JRC16_MM undef $ra, implicit killed $v0
; MM: bb.2.if.then:
- ; MM: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; MM: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MM: $v0 = LI16_MM 0
; MM: JRC16_MM undef $ra, implicit killed $v0
; PIC-LABEL: name: b
@@ -193,7 +193,7 @@ body: |
; PIC: $v0 = LI16_MM 1
; PIC: JRC16_MM undef $ra, implicit killed $v0
; PIC: bb.2.if.then:
- ; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: $v0 = LI16_MM 0
; PIC: JRC16_MM undef $ra, implicit killed $v0
bb.0.entry:
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
index 9d6713480502..aa6dfed58d5a 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir
@@ -77,7 +77,7 @@ body: |
; MM: successors: %bb.3(0x80000000)
; MM: BC_MMR6 %bb.3
; MM: bb.2.if.then:
- ; MM: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MM: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MM: $v0 = LI16_MM 0
; MM: JRC16_MM undef $ra, implicit $v0
; MM: bb.3.return:
@@ -102,7 +102,7 @@ body: |
; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: $v0 = LI16_MM 0
; PIC: JRC16_MM undef $ra, implicit $v0
; PIC: bb.4.return:
@@ -169,7 +169,7 @@ body: |
; MM: successors: %bb.3(0x80000000)
; MM: BC_MMR6 %bb.3
; MM: bb.2.if.then:
- ; MM: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MM: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MM: $v0 = LI16_MM 0
; MM: JRC16_MM undef $ra, implicit $v0
; MM: bb.3.return:
@@ -194,7 +194,7 @@ body: |
; PIC: $sp = ADDiu $sp, 8
; PIC: JIC_MMR6 $at, 0, implicit-def $at
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: $v0 = LI16_MM 0
; PIC: JRC16_MM undef $ra, implicit $v0
; PIC: bb.4.return:
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
index 802acab0619c..78d8c073ea72 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mips.mir
@@ -80,7 +80,7 @@ body: |
; MIPS: NOP
; MIPS: }
; MIPS: bb.2.if.then:
- ; MIPS: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; MIPS: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
; MIPS: $v0 = ADDiu $zero, 0
; MIPS: }
@@ -111,7 +111,7 @@ body: |
; PIC: $sp = ADDiu $sp, 8
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
; PIC: $v0 = ADDiu $zero, 0
; PIC: }
@@ -184,7 +184,7 @@ body: |
; MIPS: NOP
; MIPS: }
; MIPS: bb.2.if.then:
- ; MIPS: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; MIPS: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MIPS: PseudoReturn undef $ra, implicit killed $v0 {
; MIPS: $v0 = ADDiu $zero, 0
; MIPS: }
@@ -215,7 +215,7 @@ body: |
; PIC: $sp = ADDiu $sp, 8
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
; PIC: $v0 = ADDiu $zero, 0
; PIC: }
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
index 5356ea43485e..e472da1a93de 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir
@@ -80,7 +80,7 @@ body: |
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
; R6: bb.2.if.then:
- ; R6: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; R6: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; R6: PseudoReturn undef $ra, implicit killed $v0 {
; R6: $v0 = ADDiu $zero, 0
; R6: }
@@ -109,7 +109,7 @@ body: |
; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
; PIC: $v0 = ADDiu $zero, 0
; PIC: }
@@ -180,7 +180,7 @@ body: |
; R6: successors: %bb.3(0x80000000)
; R6: BC %bb.3
; R6: bb.2.if.then:
- ; R6: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; R6: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; R6: PseudoReturn undef $ra, implicit killed $v0 {
; R6: $v0 = ADDiu $zero, 0
; R6: }
@@ -209,7 +209,7 @@ body: |
; PIC: $sp = ADDiu $sp, 8
; PIC: JIC $at, 0, implicit-def $at
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 310680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 310680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: PseudoReturn undef $ra, implicit killed $v0 {
; PIC: $v0 = ADDiu $zero, 0
; PIC: }
diff --git a/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir b/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
index a2ceff05b857..9b497fce0a98 100644
--- a/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
+++ b/llvm/test/CodeGen/Mips/longbranch/branch-limits-msa.mir
@@ -271,7 +271,7 @@ body: |
; MSA: NOP
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; MSA: renamable $v0 = ADDiu $zero, 1
; MSA: }
@@ -307,7 +307,7 @@ body: |
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; PIC: renamable $v0 = ADDiu $zero, 1
; PIC: }
@@ -387,7 +387,7 @@ body: |
; MSA: NOP
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; MSA: renamable $v0 = ADDiu $zero, 1
; MSA: }
@@ -422,7 +422,7 @@ body: |
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; PIC: renamable $v0 = ADDiu $zero, 1
; PIC: }
@@ -501,7 +501,7 @@ body: |
; MSA: NOP
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; MSA: renamable $v0 = ADDiu $zero, 1
; MSA: }
@@ -536,7 +536,7 @@ body: |
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; PIC: renamable $v0 = ADDiu $zero, 1
; PIC: }
@@ -614,7 +614,7 @@ body: |
; MSA: NOP
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; MSA: renamable $v0 = ADDiu $zero, 1
; MSA: }
@@ -648,7 +648,7 @@ body: |
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; PIC: renamable $v0 = ADDiu $zero, 1
; PIC: }
@@ -725,7 +725,7 @@ body: |
; MSA: NOP
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; MSA: renamable $v0 = ADDiu $zero, 1
; MSA: }
@@ -759,7 +759,7 @@ body: |
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; PIC: renamable $v0 = ADDiu $zero, 1
; PIC: }
@@ -838,7 +838,7 @@ body: |
; MSA: NOP
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; MSA: renamable $v0 = ADDiu $zero, 1
; MSA: }
@@ -874,7 +874,7 @@ body: |
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; PIC: renamable $v0 = ADDiu $zero, 1
; PIC: }
@@ -954,7 +954,7 @@ body: |
; MSA: NOP
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; MSA: renamable $v0 = ADDiu $zero, 1
; MSA: }
@@ -989,7 +989,7 @@ body: |
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; PIC: renamable $v0 = ADDiu $zero, 1
; PIC: }
@@ -1068,7 +1068,7 @@ body: |
; MSA: NOP
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; MSA: renamable $v0 = ADDiu $zero, 1
; MSA: }
@@ -1103,7 +1103,7 @@ body: |
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; PIC: renamable $v0 = ADDiu $zero, 1
; PIC: }
@@ -1181,7 +1181,7 @@ body: |
; MSA: NOP
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; MSA: renamable $v0 = ADDiu $zero, 1
; MSA: }
@@ -1215,7 +1215,7 @@ body: |
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; PIC: renamable $v0 = ADDiu $zero, 1
; PIC: }
@@ -1292,7 +1292,7 @@ body: |
; MSA: NOP
; MSA: }
; MSA: bb.2.if.then:
- ; MSA: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; MSA: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; MSA: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; MSA: renamable $v0 = ADDiu $zero, 1
; MSA: }
@@ -1326,7 +1326,7 @@ body: |
; PIC: $sp_64 = DADDiu $sp_64, 16
; PIC: }
; PIC: bb.3.if.then:
- ; PIC: INLINEASM &".space 810680", 1, 12, implicit-def dead early-clobber $at
+ ; PIC: INLINEASM &".space 810680", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def dead early-clobber $at
; PIC: PseudoReturn64 undef $ra_64, implicit killed $v0 {
; PIC: renamable $v0 = ADDiu $zero, 1
; PIC: }
diff --git a/llvm/test/CodeGen/Thumb2/high-reg-spill.mir b/llvm/test/CodeGen/Thumb2/high-reg-spill.mir
index dc04b82cc0ca..ace7a38ec10b 100644
--- a/llvm/test/CodeGen/Thumb2/high-reg-spill.mir
+++ b/llvm/test/CodeGen/Thumb2/high-reg-spill.mir
@@ -41,7 +41,7 @@ body: |
; CHECK: renamable $r12 = COPY killed renamable $r0
; CHECK: t2STRi12 killed $r12, %stack.1, 0, 14 /* CC::al */, $noreg :: (store 4 into %stack.1)
; CHECK: $r8 = t2LDRi12 %stack.1, 0, 14 /* CC::al */, $noreg :: (load 4 from %stack.1)
- ; CHECK: INLINEASM &"@ $0", 1, 589833, renamable $r8, 12, implicit-def early-clobber $r12
+ ; CHECK: INLINEASM &"@ $0", 1 /* sideeffect attdialect */, 589833 /* reguse:GPRnopc */, renamable $r8, 12 /* clobber */, implicit-def early-clobber $r12
; CHECK: tBX_RET 14 /* CC::al */, $noreg
%1:tgpr = tLDRspi %stack.0.i, 0, 14, $noreg :: (dereferenceable load 4 from %ir.i)
%0:hgpr = COPY %1
diff --git a/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll b/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
index 47bbff877c56..cc647d2ba771 100644
--- a/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
+++ b/llvm/test/CodeGen/X86/inline-asm-avx512f-x-constraint.ll
@@ -2,7 +2,7 @@
; CHECK: %[[REG1:.*]]:vr512_0_15 = COPY %1
; CHECK: %[[REG2:.*]]:vr512_0_15 = COPY %2
-; CHECK: INLINEASM &"vpaddq\09$3, $2, $0 {$1}", 0, {{.*}}, def %{{.*}}, {{.*}}, %{{.*}}, {{.*}}, %[[REG1]], {{.*}}, %[[REG2]], 12, implicit-def early-clobber $df, 12, implicit-def early-clobber $fpsw, 12, implicit-def early-clobber $eflags
+; CHECK: INLINEASM &"vpaddq\09$3, $2, $0 {$1}", 0 /* attdialect */, {{.*}}, def %{{.*}}, {{.*}}, %{{.*}}, {{.*}}, %[[REG1]], {{.*}}, %[[REG2]], 12 /* clobber */, implicit-def early-clobber $df, 12 /* clobber */, implicit-def early-clobber $fpsw, 12 /* clobber */, implicit-def early-clobber $eflags
define <8 x i64> @mask_Yk_i8(i8 signext %msk, <8 x i64> %x, <8 x i64> %y) {
entry:
diff --git a/llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll b/llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll
index fae8c73cf083..4a8906af95c4 100644
--- a/llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll
+++ b/llvm/test/CodeGen/X86/inline-asm-default-clobbers.ll
@@ -1,6 +1,6 @@
; RUN: llc < %s -mtriple=i686 -stop-after=finalize-isel | FileCheck %s
-; CHECK: INLINEASM &"", 1, 12, implicit-def early-clobber $df, 12, implicit-def early-clobber $fpsw, 12, implicit-def early-clobber $eflags
+; CHECK: INLINEASM &"", 1 /* sideeffect attdialect */, 12 /* clobber */, implicit-def early-clobber $df, 12 /* clobber */, implicit-def early-clobber $fpsw, 12 /* clobber */, implicit-def early-clobber $eflags
define void @foo() {
entry:
call void asm sideeffect "", "~{dirflag},~{fpsr},~{flags}"()
diff --git a/llvm/test/CodeGen/X86/stack-folding-adx.mir b/llvm/test/CodeGen/X86/stack-folding-adx.mir
index 99e24cb12d1b..902d4b84e0c0 100644
--- a/llvm/test/CodeGen/X86/stack-folding-adx.mir
+++ b/llvm/test/CodeGen/X86/stack-folding-adx.mir
@@ -88,7 +88,7 @@ body: |
; CHECK: MOV32mr %stack.1, 1, $noreg, 0, $noreg, $edx :: (store 4 into %stack.1)
; CHECK: MOV32mr %stack.2, 1, $noreg, 0, $noreg, $esi :: (store 4 into %stack.2)
; CHECK: MOV32mr %stack.3, 1, $noreg, 0, $noreg, $edi :: (store 4 into %stack.3)
- ; CHECK: INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
+ ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 3145738 /* regdef:GR32_CB */, def dead %4, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %stack.3, 1, $noreg, 0, $noreg :: (load 4 from %stack.3)
; CHECK: dead [[MOV32rm]].sub_8bit:gr32 = ADD8ri [[MOV32rm]].sub_8bit, -1, implicit-def $eflags
; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.2, 1, $noreg, 0, $noreg :: (load 4 from %stack.2)
@@ -140,7 +140,7 @@ body: |
; CHECK: MOV64mr %stack.1, 1, $noreg, 0, $noreg, $rdx :: (store 8 into %stack.1)
; CHECK: MOV64mr %stack.2, 1, $noreg, 0, $noreg, $rsi :: (store 8 into %stack.2)
; CHECK: MOV32mr %stack.3, 1, $noreg, 0, $noreg, $edi :: (store 4 into %stack.3)
- ; CHECK: INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
+ ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 3145738 /* regdef:GR32_CB */, def dead %4, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %stack.3, 1, $noreg, 0, $noreg :: (load 4 from %stack.3)
; CHECK: dead [[MOV32rm]].sub_8bit:gr32 = ADD8ri [[MOV32rm]].sub_8bit, -1, implicit-def $eflags
; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load 8 from %stack.2)
@@ -192,7 +192,7 @@ body: |
; CHECK: MOV32mr %stack.1, 1, $noreg, 0, $noreg, $edx :: (store 4 into %stack.1)
; CHECK: MOV32mr %stack.2, 1, $noreg, 0, $noreg, $esi :: (store 4 into %stack.2)
; CHECK: MOV32mr %stack.3, 1, $noreg, 0, $noreg, $edi :: (store 4 into %stack.3)
- ; CHECK: INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
+ ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 3145738 /* regdef:GR32_CB */, def dead %4, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %stack.3, 1, $noreg, 0, $noreg :: (load 4 from %stack.3)
; CHECK: dead [[MOV32rm]].sub_8bit:gr32 = ADD8ri [[MOV32rm]].sub_8bit, 127, implicit-def $eflags
; CHECK: [[MOV32rm1:%[0-9]+]]:gr32 = MOV32rm %stack.2, 1, $noreg, 0, $noreg :: (load 4 from %stack.2)
@@ -244,7 +244,7 @@ body: |
; CHECK: MOV64mr %stack.1, 1, $noreg, 0, $noreg, $rdx :: (store 8 into %stack.1)
; CHECK: MOV64mr %stack.2, 1, $noreg, 0, $noreg, $rsi :: (store 8 into %stack.2)
; CHECK: MOV32mr %stack.3, 1, $noreg, 0, $noreg, $edi :: (store 4 into %stack.3)
- ; CHECK: INLINEASM &nop, 1, 3145738, def dead %4, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
+ ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 3145738 /* regdef:GR32_CB */, def dead %4, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
; CHECK: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm %stack.3, 1, $noreg, 0, $noreg :: (load 4 from %stack.3)
; CHECK: dead [[MOV32rm]].sub_8bit:gr32 = ADD8ri [[MOV32rm]].sub_8bit, 127, implicit-def $eflags
; CHECK: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm %stack.2, 1, $noreg, 0, $noreg :: (load 8 from %stack.2)
diff --git a/llvm/test/CodeGen/X86/stack-folding-bmi2.mir b/llvm/test/CodeGen/X86/stack-folding-bmi2.mir
index 604f7bdacdf1..8f8d074eb1b7 100644
--- a/llvm/test/CodeGen/X86/stack-folding-bmi2.mir
+++ b/llvm/test/CodeGen/X86/stack-folding-bmi2.mir
@@ -52,7 +52,7 @@ body: |
; CHECK: liveins: $edi, $esi
; CHECK: MOV32mr %stack.0, 1, $noreg, 0, $noreg, $esi :: (store 4 into %stack.0)
; CHECK: MOV32mr %stack.1, 1, $noreg, 0, $noreg, $edi :: (store 4 into %stack.1)
- ; CHECK: INLINEASM &nop, 1, 4063242, def dead %2, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
+ ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 4063242 /* regdef:LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit */, def dead %2, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
; CHECK: $edx = MOV32rm %stack.1, 1, $noreg, 0, $noreg :: (load 4 from %stack.1)
; CHECK: %3:gr32, dead %4:gr32 = MULX32rm %stack.0, 1, $noreg, 0, $noreg, implicit $edx :: (load 4 from %stack.0)
; CHECK: $eax = COPY %3
@@ -87,7 +87,7 @@ body: |
; CHECK: liveins: $rdi, $rsi
; CHECK: MOV64mr %stack.0, 1, $noreg, 0, $noreg, $rsi :: (store 8 into %stack.0)
; CHECK: MOV64mr %stack.1, 1, $noreg, 0, $noreg, $rdi :: (store 8 into %stack.1)
- ; CHECK: INLINEASM &nop, 1, 4063242, def dead %2, 12, implicit-def dead early-clobber $rax, 12, implicit-def dead early-clobber $rbx, 12, implicit-def dead early-clobber $rcx, 12, implicit-def dead early-clobber $rdx, 12, implicit-def dead early-clobber $rsi, 12, implicit-def dead early-clobber $rdi, 12, implicit-def dead early-clobber $rbp, 12, implicit-def dead early-clobber $r8, 12, implicit-def dead early-clobber $r9, 12, implicit-def dead early-clobber $r10, 12, implicit-def dead early-clobber $r11, 12, implicit-def dead early-clobber $r12, 12, implicit-def dead early-clobber $r13, 12, implicit-def dead early-clobber $r14, 12, implicit-def dead early-clobber $r15
+ ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 4063242 /* regdef:LOW32_ADDR_ACCESS_RBP_with_sub_8bit_with_sub_32bit */, def dead %2, 12 /* clobber */, implicit-def dead early-clobber $rax, 12 /* clobber */, implicit-def dead early-clobber $rbx, 12 /* clobber */, implicit-def dead early-clobber $rcx, 12 /* clobber */, implicit-def dead early-clobber $rdx, 12 /* clobber */, implicit-def dead early-clobber $rsi, 12 /* clobber */, implicit-def dead early-clobber $rdi, 12 /* clobber */, implicit-def dead early-clobber $rbp, 12 /* clobber */, implicit-def dead early-clobber $r8, 12 /* clobber */, implicit-def dead early-clobber $r9, 12 /* clobber */, implicit-def dead early-clobber $r10, 12 /* clobber */, implicit-def dead early-clobber $r11, 12 /* clobber */, implicit-def dead early-clobber $r12, 12 /* clobber */, implicit-def dead early-clobber $r13, 12 /* clobber */, implicit-def dead early-clobber $r14, 12 /* clobber */, implicit-def dead early-clobber $r15
; CHECK: $rdx = MOV64rm %stack.1, 1, $noreg, 0, $noreg :: (load 8 from %stack.1)
; CHECK: %3:gr64, dead %4:gr64 = MULX64rm %stack.0, 1, $noreg, 0, $noreg, implicit $rdx :: (load 8 from %stack.0)
; CHECK: $rax = COPY %3
diff --git a/llvm/test/CodeGen/X86/stack-folding-fp-nofpexcept.mir b/llvm/test/CodeGen/X86/stack-folding-fp-nofpexcept.mir
index 479c5d45a194..f3f945a8e54f 100644
--- a/llvm/test/CodeGen/X86/stack-folding-fp-nofpexcept.mir
+++ b/llvm/test/CodeGen/X86/stack-folding-fp-nofpexcept.mir
@@ -38,7 +38,7 @@ body: |
; CHECK: liveins: $xmm0, $xmm1
; CHECK: MOVAPSmr %stack.0, 1, $noreg, 0, $noreg, $xmm1 :: (store 16 into %stack.0)
; CHECK: [[COPY:%[0-9]+]]:vr128 = COPY $xmm0
- ; CHECK: INLINEASM &nop, 1, 7405578, def dead %2, 12, implicit-def dead early-clobber $xmm2, 12, implicit-def dead early-clobber $xmm3, 12, implicit-def dead early-clobber $xmm4, 12, implicit-def dead early-clobber $xmm5, 12, implicit-def dead early-clobber $xmm6, 12, implicit-def dead early-clobber $xmm7, 12, implicit-def dead early-clobber $xmm8, 12, implicit-def dead early-clobber $xmm9, 12, implicit-def dead early-clobber $xmm10, 12, implicit-def dead early-clobber $xmm11, 12, implicit-def dead early-clobber $xmm12, 12, implicit-def dead early-clobber $xmm13, 12, implicit-def dead early-clobber $xmm14, 12, implicit-def dead early-clobber $xmm15, 12, implicit-def dead early-clobber $eflags
+ ; CHECK: INLINEASM &nop, 1 /* sideeffect attdialect */, 7405578 /* regdef:VR128 */, def dead %2, 12 /* clobber */, implicit-def dead early-clobber $xmm2, 12 /* clobber */, implicit-def dead early-clobber $xmm3, 12 /* clobber */, implicit-def dead early-clobber $xmm4, 12 /* clobber */, implicit-def dead early-clobber $xmm5, 12 /* clobber */, implicit-def dead early-clobber $xmm6, 12 /* clobber */, implicit-def dead early-clobber $xmm7, 12 /* clobber */, implicit-def dead early-clobber $xmm8, 12 /* clobber */, implicit-def dead early-clobber $xmm9, 12 /* clobber */, implicit-def dead early-clobber $xmm10, 12 /* clobber */, implicit-def dead early-clobber $xmm11, 12 /* clobber */, implicit-def dead early-clobber $xmm12, 12 /* clobber */, implicit-def dead early-clobber $xmm13, 12 /* clobber */, implicit-def dead early-clobber $xmm14, 12 /* clobber */, implicit-def dead early-clobber $xmm15, 12 /* clobber */, implicit-def dead early-clobber $eflags
; CHECK: [[COPY]]:vr128 = nofpexcept ADDPDrm [[COPY]], %stack.0, 1, $noreg, 0, $noreg, implicit $mxcsr :: (load 16 from %stack.0)
; CHECK: $xmm0 = COPY [[COPY]]
; CHECK: RET 0, $xmm0
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