[PATCH] D78278: [CodeGen] Support freeze expand for ppc_fp128
Zhang Kang via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Apr 16 00:54:21 PDT 2020
ZhangKang created this revision.
ZhangKang added reviewers: PowerPC, hfinkel, kbarton, qcolombet, efriedma, lebedev.ri, craig.topper, arsenm, aqjune, mkuper, bkramer, nemanjai.
ZhangKang added a project: LLVM.
Herald added subscribers: wuzish, hiraditya, wdng.
The patch https://reviews.llvm.org/D29014 has added the new ISD::FREEZE and can deal with the integer.
The patch https://reviews.llvm.org/D76980 has added SoftenFloatRes_FREEZE for float point.
But from below code, we can know ppc_fp128, it should expand.
1193 // ppcf128 type is really two f64's.
1194 if (!isTypeLegal(MVT::ppcf128)) {
1195 if (isTypeLegal(MVT::f64)) {
1196 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1197 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1198 TransformToType[MVT::ppcf128] = MVT::f64;
1199 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1200 } else {
1201 NumRegistersForVT[MVT::ppcf128] = NumRegistersForVT[MVT::i128];
1202 RegisterTypeForVT[MVT::ppcf128] = RegisterTypeForVT[MVT::i128];
1203 TransformToType[MVT::ppcf128] = MVT::i128;
1204 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeSoftenFloat);
1205 }
1206 }
Some cases have gotten assertion for lack of expand for ppc_fp128. For example, below case:
`cat ppcf128.mir`
--- |
define ppc_fp128 @freeze_select(ppc_fp128 %a, ppc_fp128 %b) {
%sel.frozen = freeze ppc_fp128 %a
%cmp = fcmp one ppc_fp128 %sel.frozen, 0xM00000000000000000000000000000000
br i1 %cmp, label %select.end, label %select.false
select.false: ; preds = %0
br label %select.end
select.end: ; preds = %0, %select.false
%sel = phi ppc_fp128 [ %a, %0 ], [ %b, %select.false ]
ret ppc_fp128 %sel
}
...
Using below command:
llc -mtriple powerpc64le-unknown-linux-gnu -start-after=codegenprepare ppcf128.mir
You will get below error:
ExpandFloatResult #0: t33: ppcf128 = freeze t9
Do not know how to expand the result of this operator!
UNREACHABLE executed at /home/shkzhang/llvm/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp:1122!
This patch is to support freeze expand for ppc_fp128 to fix the above error.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D78278
Files:
llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
llvm/test/CodeGen/PowerPC/ppcf128.mir
Index: llvm/test/CodeGen/PowerPC/ppcf128.mir
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/PowerPC/ppcf128.mir
@@ -0,0 +1,35 @@
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -start-after=codegenprepare \
+# RUN: -o - %s -verify-machineinstrs | FileCheck %s
+
+--- |
+ define ppc_fp128 @freeze_select(ppc_fp128 %a, ppc_fp128 %b) {
+ %sel.frozen = freeze ppc_fp128 %a
+ %cmp = fcmp one ppc_fp128 %sel.frozen, 0xM00000000000000000000000000000000
+ br i1 %cmp, label %select.end, label %select.false
+
+ select.false: ; preds = %0
+ br label %select.end
+
+ select.end: ; preds = %0, %select.false
+ %sel = phi ppc_fp128 [ %a, %0 ], [ %b, %select.false ]
+ ret ppc_fp128 %sel
+ }
+
+ ; CHECK-LABEL: freeze_select
+ ; CHECK: # %bb.0:
+ ; CHECK-NEXT: xxlxor 0, 0, 0
+ ; CHECK-NEXT: fcmpu 5, 2, 2
+ ; CHECK-NEXT: fcmpu 1, 1, 1
+ ; CHECK-NEXT: fcmpu 6, 2, 0
+ ; CHECK-NEXT: fcmpu 0, 1, 0
+ ; CHECK-NEXT: crnor 20, 23, 26
+ ; CHECK-NEXT: crand 20, 2, 20
+ ; CHECK-NEXT: bclr 12, 20, 0
+ ; CHECK-NEXT: # %bb.1:
+ ; CHECK-NEXT: crnor 20, 7, 2
+ ; CHECK-NEXT: bclr 12, 20, 0
+ ; CHECK-NEXT: # %bb.2: # %select.false
+ ; CHECK-NEXT: fmr 1, 3
+ ; CHECK-NEXT: fmr 2, 4
+ ; CHECK-NEXT: blr
+...
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -599,6 +599,7 @@
void ExpandFloatRes_FP_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FPOW (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FPOWI (SDNode *N, SDValue &Lo, SDValue &Hi);
+ void ExpandFloatRes_FREEZE (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FREM (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FRINT (SDNode *N, SDValue &Lo, SDValue &Hi);
void ExpandFloatRes_FROUND (SDNode *N, SDValue &Lo, SDValue &Hi);
Index: llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -1173,6 +1173,7 @@
case ISD::FPOW: ExpandFloatRes_FPOW(N, Lo, Hi); break;
case ISD::STRICT_FPOWI:
case ISD::FPOWI: ExpandFloatRes_FPOWI(N, Lo, Hi); break;
+ case ISD::FREEZE: ExpandFloatRes_FREEZE(N, Lo, Hi); break;
case ISD::STRICT_FRINT:
case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break;
case ISD::STRICT_FROUND:
@@ -1466,6 +1467,17 @@
RTLIB::POWI_PPCF128), Lo, Hi);
}
+void DAGTypeLegalizer::ExpandFloatRes_FREEZE(SDNode *N,
+ SDValue &Lo, SDValue &Hi) {
+ assert(N->getValueType(0) == MVT::ppcf128 &&
+ "Logic only correct for ppcf128!");
+
+ SDLoc dl(N);
+ GetExpandedFloat(N->getOperand(0), Lo, Hi);
+ Lo = DAG.getNode(ISD::FREEZE, dl, Lo.getValueType(), Lo);
+ Hi = DAG.getNode(ISD::FREEZE, dl, Hi.getValueType(), Hi);
+}
+
void DAGTypeLegalizer::ExpandFloatRes_FREM(SDNode *N,
SDValue &Lo, SDValue &Hi) {
ExpandFloatRes_Binary(N, GetFPLibCall(N->getValueType(0),
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