[PATCH] D78091: [AMDGPU] Enable carry out ADD/SUB operations divergence driven instruction selection.

[Stanislav Mekhanoshin via Phabricator via llvm-commits]

rampitec added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:3695
+
+    const TargetRegisterClass *Src0RC = MRI.getRegClass(Src0.getReg());
+    const TargetRegisterClass *Src1RC = Src1.isReg()
----------------
Either operand can be immediate.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:3698
+                                            ? MRI.getRegClass(Src1.getReg())
+                                            : &AMDGPU::VGPR_32RegClass;
+    const TargetRegisterClass *Src0SubRC =
----------------
VReg_64? Since it did not fail anywhere this case must be not covered by any tests.


================
Comment at: llvm/lib/Target/AMDGPU/SIISelLowering.cpp:3757
+                       : AMDGPU::S_SUBB_U32;
+    if (TRI->isVectorRegister(MRI, Src0.getReg())) {
+      Register RegOp0 = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass);
----------------
Again it can be an immediate.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:5193
+              .addReg(DummyCReg, RegState::Define | RegState::Dead)
+              .addReg(Inst.getOperand(2).getReg())
+              .addReg(Inst.getOperand(3).getReg())
----------------
These are not necessarily registers too.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:5220
+              .addReg(Dest1.getReg(), RegState::Define)
+              .addReg(Src0.getReg());
+      if (Src1.isReg())
----------------
Same here.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:5973
+        SmallVector<MachineInstr *, 4> Users;
+        for (auto &User : MRI.use_instructions(DestReg)) {
+          if ((User.getOpcode() == AMDGPU::S_ADD_CO_PSEUDO) ||
----------------
use_nodbg_instructions()


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D78091/new/

https://reviews.llvm.org/D78091